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LU-JOHNLU-JOHN
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Avoid copying MachineOperands
Signed-off-by: John Lu <John.Lu@amd.com>
1 parent bb14b83 commit 40f4044

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6 files changed

+64
-60
lines changed

6 files changed

+64
-60
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -469,10 +469,14 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
469469
const TargetRegisterClass &HalfRC
470470
= IsSALU ? AMDGPU::SReg_32RegClass : AMDGPU::VGPR_32RegClass;
471471

472-
MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0));
473-
MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0));
474-
MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
475-
MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1));
472+
const MachineOperand &Lo1(
473+
getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0));
474+
const MachineOperand &Lo2(
475+
getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0));
476+
const MachineOperand &Hi1(
477+
getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
478+
const MachineOperand &Hi2(
479+
getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1));
476480

477481
Register DstLo = MRI->createVirtualRegister(&HalfRC);
478482
Register DstHi = MRI->createVirtualRegister(&HalfRC);
@@ -6753,7 +6757,7 @@ bool AMDGPUInstructionSelector::selectSGetBarrierState(
67536757
MachineInstr &I, Intrinsic::ID IntrID) const {
67546758
MachineBasicBlock *MBB = I.getParent();
67556759
const DebugLoc &DL = I.getDebugLoc();
6756-
MachineOperand BarOp = I.getOperand(2);
6760+
const MachineOperand &BarOp = I.getOperand(2);
67576761
std::optional<int64_t> BarValImm =
67586762
getIConstantVRegSExtVal(BarOp.getReg(), *MRI);
67596763

@@ -6806,8 +6810,8 @@ bool AMDGPUInstructionSelector::selectNamedBarrierInit(
68066810
MachineInstr &I, Intrinsic::ID IntrID) const {
68076811
MachineBasicBlock *MBB = I.getParent();
68086812
const DebugLoc &DL = I.getDebugLoc();
6809-
MachineOperand BarOp = I.getOperand(1);
6810-
MachineOperand CntOp = I.getOperand(2);
6813+
const MachineOperand &BarOp = I.getOperand(1);
6814+
const MachineOperand &CntOp = I.getOperand(2);
68116815

68126816
// BarID = (BarOp >> 4) & 0x3F
68136817
Register TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);

‎llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ bool GCNPreRAOptimizationsImpl::processReg(Register Reg) {
136136
continue;
137137

138138
if (Def.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64) {
139-
MachineOperand DefSrcMO = Def.getOperand(1);
139+
const MachineOperand &DefSrcMO = Def.getOperand(1);
140140

141141
// Immediates are not an issue and can be propagated in
142142
// postrapseudos pass. Only handle cases where defining

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -5435,14 +5435,14 @@ static MachineBasicBlock *Expand64BitScalarArithmetic(MachineInstr &MI,
54355435
Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
54365436
Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
54375437

5438-
MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
5438+
const MachineOperand &Src0Sub0 = TII->buildExtractSubRegOrImm(
54395439
MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
5440-
MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
5440+
const MachineOperand &Src0Sub1 = TII->buildExtractSubRegOrImm(
54415441
MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
54425442

5443-
MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
5443+
const MachineOperand &Src1Sub0 = TII->buildExtractSubRegOrImm(
54445444
MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
5445-
MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
5445+
const MachineOperand &Src1Sub1 = TII->buildExtractSubRegOrImm(
54465446
MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
54475447

54485448
unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
@@ -5603,9 +5603,9 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
56035603
const TargetRegisterClass *SrcSubRC =
56045604
TRI->getSubRegisterClass(SrcRC, AMDGPU::sub0);
56055605

5606-
MachineOperand Op1L = TII->buildExtractSubRegOrImm(
5606+
const MachineOperand &Op1L = TII->buildExtractSubRegOrImm(
56075607
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub0, SrcSubRC);
5608-
MachineOperand Op1H = TII->buildExtractSubRegOrImm(
5608+
const MachineOperand &Op1H = TII->buildExtractSubRegOrImm(
56095609
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub1, SrcSubRC);
56105610

56115611
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DestSub0)
@@ -5661,9 +5661,9 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
56615661
const TargetRegisterClass *Src1SubRC =
56625662
TRI->getSubRegisterClass(Src1RC, AMDGPU::sub0);
56635663

5664-
MachineOperand Op1L = TII->buildExtractSubRegOrImm(
5664+
const MachineOperand &Op1L = TII->buildExtractSubRegOrImm(
56655665
MI, MRI, MI.getOperand(1), Src1RC, AMDGPU::sub0, Src1SubRC);
5666-
MachineOperand Op1H = TII->buildExtractSubRegOrImm(
5666+
const MachineOperand &Op1H = TII->buildExtractSubRegOrImm(
56675667
MI, MRI, MI.getOperand(1), Src1RC, AMDGPU::sub1, Src1SubRC);
56685668

56695669
if (Opc == AMDGPU::S_SUB_U64_PSEUDO) {
@@ -5799,9 +5799,9 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
57995799
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
58005800
const TargetRegisterClass *SrcSubRC =
58015801
TRI->getSubRegisterClass(SrcRC, AMDGPU::sub0);
5802-
MachineOperand Op1L = TII->buildExtractSubRegOrImm(
5802+
const MachineOperand &Op1L = TII->buildExtractSubRegOrImm(
58035803
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub0, SrcSubRC);
5804-
MachineOperand Op1H = TII->buildExtractSubRegOrImm(
5804+
const MachineOperand &Op1H = TII->buildExtractSubRegOrImm(
58055805
MI, MRI, MI.getOperand(1), SrcRC, AMDGPU::sub1, SrcSubRC);
58065806
// lane value input should be in an sgpr
58075807
BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READLANE_B32),
@@ -5839,10 +5839,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
58395839
const TargetRegisterClass *VSubRegClass =
58405840
TRI->getSubRegisterClass(VregClass, AMDGPU::sub0);
58415841
Register AccumulatorVReg = MRI.createVirtualRegister(VregClass);
5842-
MachineOperand SrcReg0Sub0 =
5842+
const MachineOperand &SrcReg0Sub0 =
58435843
TII->buildExtractSubRegOrImm(MI, MRI, Accumulator->getOperand(0),
58445844
VregClass, AMDGPU::sub0, VSubRegClass);
5845-
MachineOperand SrcReg0Sub1 =
5845+
const MachineOperand &SrcReg0Sub1 =
58465846
TII->buildExtractSubRegOrImm(MI, MRI, Accumulator->getOperand(0),
58475847
VregClass, AMDGPU::sub1, VSubRegClass);
58485848
BuildMI(*ComputeLoop, I, DL, TII->get(TargetOpcode::REG_SEQUENCE),
@@ -6028,14 +6028,14 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
60286028
const TargetRegisterClass *Src1SubRC =
60296029
TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1);
60306030

6031-
MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
6031+
const MachineOperand &SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
60326032
MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
6033-
MachineOperand SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
6033+
const MachineOperand &SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
60346034
MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
60356035

6036-
MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
6036+
const MachineOperand &SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
60376037
MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
6038-
MachineOperand SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
6038+
const MachineOperand &SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
60396039
MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
60406040

60416041
unsigned LoOpc =
@@ -6104,9 +6104,9 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
61046104
const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg());
61056105
const TargetRegisterClass *SubRC =
61066106
TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0);
6107-
MachineOperand Src2Sub0 = TII->buildExtractSubRegOrImm(
6107+
const MachineOperand &Src2Sub0 = TII->buildExtractSubRegOrImm(
61086108
MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
6109-
MachineOperand Src2Sub1 = TII->buildExtractSubRegOrImm(
6109+
const MachineOperand &Src2Sub1 = TII->buildExtractSubRegOrImm(
61106110
MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
61116111
Register Src2_32 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
61126112

@@ -6252,14 +6252,14 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
62526252
const TargetRegisterClass *Src1SubRC =
62536253
TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1);
62546254

6255-
MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
6255+
const MachineOperand &Src0Sub0 = TII->buildExtractSubRegOrImm(
62566256
MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
6257-
MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
6257+
const MachineOperand &Src1Sub0 = TII->buildExtractSubRegOrImm(
62586258
MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
62596259

6260-
MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
6260+
const MachineOperand &Src0Sub1 = TII->buildExtractSubRegOrImm(
62616261
MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
6262-
MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
6262+
const MachineOperand &Src1Sub1 = TII->buildExtractSubRegOrImm(
62636263
MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
62646264

62656265
BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy).addReg(SrcCond);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -7945,7 +7945,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
79457945
}
79467946
legalizeOperands(*NewInstr, MDT);
79477947
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
7948-
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
7948+
const MachineOperand &SCCOp = Inst.getOperand(SCCIdx);
79497949
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
79507950
Inst.eraseFromParent();
79517951
return;
@@ -7985,7 +7985,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
79857985
legalizeOperandsVALUt16(*NewInstr, MRI);
79867986
legalizeOperands(*NewInstr, MDT);
79877987
int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr);
7988-
MachineOperand SCCOp = Inst.getOperand(SCCIdx);
7988+
const MachineOperand &SCCOp = Inst.getOperand(SCCIdx);
79897989
addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);
79907990
Inst.eraseFromParent();
79917991
return;
@@ -8183,7 +8183,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
81838183
AMDGPU::OpName::src0_modifiers) >= 0)
81848184
NewInstr.addImm(0);
81858185
if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::src0)) {
8186-
MachineOperand Src = Inst.getOperand(1);
8186+
const MachineOperand &Src = Inst.getOperand(1);
81878187
NewInstr->addOperand(Src);
81888188
}
81898189

@@ -8555,8 +8555,8 @@ void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,
85558555
const TargetRegisterClass *Src0SubRC =
85568556
RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
85578557

8558-
MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8559-
AMDGPU::sub0, Src0SubRC);
8558+
const MachineOperand &SrcReg0Sub0 =
8559+
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
85608560

85618561
const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
85628562
const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
@@ -8566,8 +8566,8 @@ void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,
85668566
Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
85678567
MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
85688568

8569-
MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8570-
AMDGPU::sub1, Src0SubRC);
8569+
const MachineOperand &SrcReg0Sub1 =
8570+
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
85718571

85728572
Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
85738573
MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
@@ -8625,13 +8625,13 @@ void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist,
86258625

86268626
// First, we extract the low 32-bit and high 32-bit values from each of the
86278627
// operands.
8628-
MachineOperand Op0L =
8628+
const MachineOperand &Op0L =
86298629
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8630-
MachineOperand Op1L =
8630+
const MachineOperand &Op1L =
86318631
buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
8632-
MachineOperand Op0H =
8632+
const MachineOperand &Op0H =
86338633
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
8634-
MachineOperand Op1H =
8634+
const MachineOperand &Op1H =
86358635
buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
86368636

86378637
// The multilication is done as follows:
@@ -8734,9 +8734,9 @@ void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist,
87348734

87358735
// First, we extract the low 32-bit and high 32-bit values from each of the
87368736
// operands.
8737-
MachineOperand Op0L =
8737+
const MachineOperand &Op0L =
87388738
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8739-
MachineOperand Op1L =
8739+
const MachineOperand &Op1L =
87408740
buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
87418741

87428742
unsigned Opc = Inst.getOpcode();
@@ -8795,14 +8795,14 @@ void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist,
87958795
const TargetRegisterClass *Src1SubRC =
87968796
RI.getSubRegisterClass(Src1RC, AMDGPU::sub0);
87978797

8798-
MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8799-
AMDGPU::sub0, Src0SubRC);
8800-
MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
8801-
AMDGPU::sub0, Src1SubRC);
8802-
MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8803-
AMDGPU::sub1, Src0SubRC);
8804-
MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
8805-
AMDGPU::sub1, Src1SubRC);
8798+
const MachineOperand &SrcReg0Sub0 =
8799+
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8800+
const MachineOperand &SrcReg1Sub0 =
8801+
buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
8802+
const MachineOperand &SrcReg0Sub1 =
8803+
buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
8804+
const MachineOperand &SrcReg1Sub1 =
8805+
buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
88068806

88078807
const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
88088808
const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
@@ -8899,10 +8899,10 @@ void SIInstrInfo::splitScalar64BitBCNT(SIInstrWorklist &Worklist,
88998899
const TargetRegisterClass *SrcSubRC =
89008900
RI.getSubRegisterClass(SrcRC, AMDGPU::sub0);
89018901

8902-
MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
8903-
AMDGPU::sub0, SrcSubRC);
8904-
MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
8905-
AMDGPU::sub1, SrcSubRC);
8902+
const MachineOperand &SrcRegSub0 =
8903+
buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub0, SrcSubRC);
8904+
const MachineOperand &SrcRegSub1 =
8905+
buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub1, SrcSubRC);
89068906

89078907
BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
89088908

@@ -9003,9 +9003,9 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,
90039003
const TargetRegisterClass *SrcSubRC =
90049004
RI.getSubRegisterClass(SrcRC, AMDGPU::sub0);
90059005

9006-
MachineOperand SrcRegSub0 =
9006+
const MachineOperand &SrcRegSub0 =
90079007
buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub0, SrcSubRC);
9008-
MachineOperand SrcRegSub1 =
9008+
const MachineOperand &SrcRegSub1 =
90099009
buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, AMDGPU::sub1, SrcSubRC);
90109010

90119011
Register MidReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
@@ -9199,7 +9199,7 @@ void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,
91999199
addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
92009200
}
92019201

9202-
void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
9202+
void SIInstrInfo::addSCCDefUsersToVALUWorklist(const MachineOperand &Op,
92039203
MachineInstr &SCCDefInst,
92049204
SIInstrWorklist &Worklist,
92059205
Register NewCond) const {

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
172172
void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
173173
SIInstrWorklist &Worklist) const;
174174

175-
void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
175+
void addSCCDefUsersToVALUWorklist(const MachineOperand &Op,
176176
MachineInstr &SCCDefInst,
177177
SIInstrWorklist &Worklist,
178178
Register NewCond = Register()) const;

‎llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -640,7 +640,7 @@ void SIPreEmitPeephole::collectUnpackingCandidates(
640640
}
641641

642642
void SIPreEmitPeephole::performF32Unpacking(MachineInstr &I) {
643-
MachineOperand DstOp = I.getOperand(0);
643+
const MachineOperand &DstOp = I.getOperand(0);
644644

645645
uint16_t UnpackedOpcode = mapToUnpackedOpcode(I);
646646
assert(UnpackedOpcode != std::numeric_limits<uint16_t>::max() &&

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