@@ -1005,24 +1005,22 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
10051005
10061006 // Fold the operation. Leave any dead instructions for DCE to clean up.
10071007 if (FoldedOpc) {
1008- // NewVReg might be XZR/WZR. In that case create a COPY into a virtual
1009- // register.
1010- if (!Register::isVirtualRegister (NewReg)) {
1011- unsigned ZeroReg = NewReg;
1012- NewReg = MRI.createVirtualRegister (RC);
1013- BuildMI (MBB, I, DL, get (TargetOpcode::COPY), NewReg).addReg (ZeroReg);
1014- }
1015-
10161008 FalseReg = NewReg;
10171009 Opc = FoldedOpc;
1018- // The extends the live range of NewVReg .
1010+ // Extend the live range of NewReg .
10191011 MRI.clearKillFlags (NewReg);
10201012 }
10211013 }
10221014
10231015 // Pull all virtual register into the appropriate class.
10241016 MRI.constrainRegClass (TrueReg, RC);
1025- MRI.constrainRegClass (FalseReg, RC);
1017+ // FalseReg might be WZR or XZR if the folded operand is a literal 1.
1018+ assert (
1019+ (FalseReg.isVirtual () || FalseReg == AArch64::WZR ||
1020+ FalseReg == AArch64::XZR) &&
1021+ " FalseReg was folded into a non-virtual register other than WZR or XZR" );
1022+ if (FalseReg.isVirtual ())
1023+ MRI.constrainRegClass (FalseReg, RC);
10261024
10271025 // Insert the csel.
10281026 BuildMI (MBB, I, DL, get (Opc), DstReg)
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