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[RISCV] Custom promote f16 (l)lround/(l)lrint with Zfhmin/Zhinxmin instead of using isel patterns.
1 parent 776aef1 commit 357bd61

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2 files changed

+27
-32
lines changed

2 files changed

+27
-32
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 27 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -473,9 +473,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
473473
setOperationAction(ISD::IS_FPCLASS, MVT::f16, Custom);
474474
} else {
475475
setOperationAction(ZfhminZfbfminPromoteOps, MVT::f16, Promote);
476-
setOperationAction({ISD::STRICT_LRINT, ISD::STRICT_LLRINT,
477-
ISD::STRICT_LROUND, ISD::STRICT_LLROUND},
478-
MVT::f16, Legal);
476+
for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
477+
ISD::STRICT_LROUND, ISD::STRICT_LLROUND,
478+
ISD::STRICT_LRINT, ISD::STRICT_LLRINT})
479+
setOperationAction(Op, MVT::f16, Custom);
479480
setOperationAction(ISD::FABS, MVT::f16, Custom);
480481
setOperationAction(ISD::FNEG, MVT::f16, Custom);
481482
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
@@ -6781,7 +6782,29 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
67816782
return lowerFTRUNC_FCEIL_FFLOOR_FROUND(Op, DAG, Subtarget);
67826783
case ISD::LRINT:
67836784
case ISD::LLRINT:
6784-
return lowerVectorXRINT(Op, DAG, Subtarget);
6785+
if (Op.getValueType().isVector())
6786+
return lowerVectorXRINT(Op, DAG, Subtarget);
6787+
[[fallthrough]];
6788+
case ISD::LROUND:
6789+
case ISD::LLROUND: {
6790+
assert(Op.getOperand(0).getValueType() == MVT::f16 &&
6791+
"Unexpected custom legalisation");
6792+
SDLoc DL(Op);
6793+
SDValue Ext = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0));
6794+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(), Ext);
6795+
}
6796+
case ISD::STRICT_LRINT:
6797+
case ISD::STRICT_LLRINT:
6798+
case ISD::STRICT_LROUND:
6799+
case ISD::STRICT_LLROUND: {
6800+
assert(Op.getOperand(1).getValueType() == MVT::f16 &&
6801+
"Unexpected custom legalisation");
6802+
SDLoc DL(Op);
6803+
SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
6804+
{Op.getOperand(0), Op.getOperand(1)});
6805+
return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
6806+
{Ext.getValue(1), Ext.getValue(0)});
6807+
}
67856808
case ISD::VECREDUCE_ADD:
67866809
case ISD::VECREDUCE_UMAX:
67876810
case ISD::VECREDUCE_SMAX:

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -605,12 +605,6 @@ let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
605605
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
606606
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
607607

608-
// half->int32 with current rounding mode.
609-
def : Pat<(i32 (any_lrint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_DYN)>;
610-
611-
// half->int32 rounded to nearest with ties rounded away from zero.
612-
def : Pat<(i32 (any_lround (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RMM)>;
613-
614608
// [u]int->half. Match GCC and default to using dynamic rounding mode.
615609
def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
616610
def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
@@ -621,12 +615,6 @@ let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
621615
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
622616
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
623617

624-
// half->int32 with current rounding mode.
625-
def : Pat<(i32 (any_lrint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_DYN)>;
626-
627-
// half->int32 rounded to nearest with ties rounded away from zero.
628-
def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RMM)>;
629-
630618
// [u]int->half. Match GCC and default to using dynamic rounding mode.
631619
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_W_INX $rs1, FRM_DYN), FRM_DYN)>;
632620
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_WU_INX $rs1, FRM_DYN), FRM_DYN)>;
@@ -637,14 +625,6 @@ let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
637625
def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
638626
def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
639627

640-
// half->int64 with current rounding mode.
641-
def : Pat<(i64 (any_lrint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_DYN)>;
642-
def : Pat<(i64 (any_llrint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_DYN)>;
643-
644-
// half->int64 rounded to nearest with ties rounded away from zero.
645-
def : Pat<(i64 (any_lround (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RMM)>;
646-
def : Pat<(i64 (any_llround (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RMM)>;
647-
648628
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
649629
def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
650630
def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
@@ -655,14 +635,6 @@ let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
655635
def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
656636
def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
657637

658-
// half->int64 with current rounding mode.
659-
def : Pat<(i64 (any_lrint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_DYN)>;
660-
def : Pat<(i64 (any_llrint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_DYN)>;
661-
662-
// half->int64 rounded to nearest with ties rounded away from zero.
663-
def : Pat<(i64 (any_lround FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RMM)>;
664-
def : Pat<(i64 (any_llround FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RMM)>;
665-
666638
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
667639
def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_L_INX $rs1, FRM_DYN), FRM_DYN)>;
668640
def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_LU_INX $rs1, FRM_DYN), FRM_DYN)>;

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