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[mips] Implement sge/sgeu pseudo instructions
The `sge/sgeu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than or equal `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64314 llvm-svn: 365476
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‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp‎

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,12 @@ class MipsAsmParser : public MCTargetAsmParser {
275275
bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
276276
const MCSubtargetInfo *STI);
277277

278+
bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
279+
const MCSubtargetInfo *STI);
280+
281+
bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
282+
const MCSubtargetInfo *STI);
283+
278284
bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
279285
const MCSubtargetInfo *STI);
280286

@@ -2476,6 +2482,14 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
24762482
case Mips::NORImm:
24772483
case Mips::NORImm64:
24782484
return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2485+
case Mips::SGE:
2486+
case Mips::SGEU:
2487+
return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2488+
case Mips::SGEImm:
2489+
case Mips::SGEUImm:
2490+
case Mips::SGEImm64:
2491+
case Mips::SGEUImm64:
2492+
return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
24792493
case Mips::SGTImm:
24802494
case Mips::SGTUImm:
24812495
case Mips::SGTImm64:
@@ -4293,6 +4307,96 @@ bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
42934307
return false;
42944308
}
42954309

4310+
bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4311+
const MCSubtargetInfo *STI) {
4312+
MipsTargetStreamer &TOut = getTargetStreamer();
4313+
4314+
assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4315+
assert(Inst.getOperand(0).isReg() &&
4316+
Inst.getOperand(1).isReg() &&
4317+
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
4318+
4319+
unsigned DstReg = Inst.getOperand(0).getReg();
4320+
unsigned SrcReg = Inst.getOperand(1).getReg();
4321+
unsigned OpReg = Inst.getOperand(2).getReg();
4322+
unsigned OpCode;
4323+
4324+
warnIfNoMacro(IDLoc);
4325+
4326+
switch (Inst.getOpcode()) {
4327+
case Mips::SGE:
4328+
OpCode = Mips::SLT;
4329+
break;
4330+
case Mips::SGEU:
4331+
OpCode = Mips::SLTu;
4332+
break;
4333+
default:
4334+
llvm_unreachable("unexpected 'sge' opcode");
4335+
}
4336+
4337+
// $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
4338+
TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4339+
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4340+
4341+
return false;
4342+
}
4343+
4344+
bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4345+
const MCSubtargetInfo *STI) {
4346+
MipsTargetStreamer &TOut = getTargetStreamer();
4347+
4348+
assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4349+
assert(Inst.getOperand(0).isReg() &&
4350+
Inst.getOperand(1).isReg() &&
4351+
Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4352+
4353+
unsigned DstReg = Inst.getOperand(0).getReg();
4354+
unsigned SrcReg = Inst.getOperand(1).getReg();
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int64_t ImmValue = Inst.getOperand(2).getImm();
4356+
unsigned OpRegCode, OpImmCode;
4357+
4358+
warnIfNoMacro(IDLoc);
4359+
4360+
switch (Inst.getOpcode()) {
4361+
case Mips::SGEImm:
4362+
case Mips::SGEImm64:
4363+
OpRegCode = Mips::SLT;
4364+
OpImmCode = Mips::SLTi;
4365+
break;
4366+
case Mips::SGEUImm:
4367+
case Mips::SGEUImm64:
4368+
OpRegCode = Mips::SLTu;
4369+
OpImmCode = Mips::SLTiu;
4370+
break;
4371+
default:
4372+
llvm_unreachable("unexpected 'sge' opcode with immediate");
4373+
}
4374+
4375+
// $SrcReg >= Imm is equal to (not ($SrcReg < Imm))
4376+
if (isInt<16>(ImmValue)) {
4377+
// Use immediate version of STL.
4378+
TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
4379+
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4380+
} else {
4381+
unsigned ImmReg = DstReg;
4382+
if (DstReg == SrcReg) {
4383+
unsigned ATReg = getATReg(Inst.getLoc());
4384+
if (!ATReg)
4385+
return true;
4386+
ImmReg = ATReg;
4387+
}
4388+
4389+
if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4390+
false, IDLoc, Out, STI))
4391+
return true;
4392+
4393+
TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4394+
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4395+
}
4396+
4397+
return false;
4398+
}
4399+
42964400
bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
42974401
const MCSubtargetInfo *STI) {
42984402
MipsTargetStreamer &TOut = getTargetStreamer();

‎llvm/lib/Target/Mips/Mips64InstrInfo.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,6 +1155,20 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs),
11551155
def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
11561156
imm64:$imm)>, GPR_64;
11571157

1158+
def SGEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
1159+
(ins GPR64Opnd:$rs, imm64:$imm),
1160+
"sge\t$rd, $rs, $imm">, GPR_64;
1161+
def : MipsInstAlias<"sge $rs, $imm", (SGEImm64 GPR64Opnd:$rs,
1162+
GPR64Opnd:$rs,
1163+
imm64:$imm), 0>, GPR_64;
1164+
1165+
def SGEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
1166+
(ins GPR64Opnd:$rs, imm64:$imm),
1167+
"sgeu\t$rd, $rs, $imm">, GPR_64;
1168+
def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm64 GPR64Opnd:$rs,
1169+
GPR64Opnd:$rs,
1170+
imm64:$imm), 0>, GPR_64;
1171+
11581172
def SGTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
11591173
(ins GPR64Opnd:$rs, imm64:$imm),
11601174
"sgt\t$rd, $rs, $imm">, GPR_64;

‎llvm/lib/Target/Mips/MipsInstrInfo.td‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2693,6 +2693,35 @@ let AdditionalPredicates = [NotInMicroMips] in {
26932693
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS1;
26942694
def : MipsInstAlias<"negu $rt",
26952695
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;
2696+
2697+
def SGE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2698+
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2699+
"sge\t$rd, $rs, $rt">, ISA_MIPS1;
2700+
def : MipsInstAlias<"sge $rs, $rt",
2701+
(SGE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
2702+
ISA_MIPS1;
2703+
def SGEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2704+
(ins GPR32Opnd:$rs, simm32:$imm),
2705+
"sge\t$rd, $rs, $imm">, GPR_32;
2706+
def : MipsInstAlias<"sge $rs, $imm", (SGEImm GPR32Opnd:$rs,
2707+
GPR32Opnd:$rs,
2708+
simm32:$imm), 0>,
2709+
GPR_32;
2710+
2711+
def SGEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2712+
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2713+
"sgeu\t$rd, $rs, $rt">, ISA_MIPS1;
2714+
def : MipsInstAlias<"sgeu $rs, $rt",
2715+
(SGEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
2716+
ISA_MIPS1;
2717+
def SGEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2718+
(ins GPR32Opnd:$rs, uimm32_coerced:$imm),
2719+
"sgeu\t$rd, $rs, $imm">, GPR_32;
2720+
def : MipsInstAlias<"sgeu $rs, $imm", (SGEUImm GPR32Opnd:$rs,
2721+
GPR32Opnd:$rs,
2722+
uimm32_coerced:$imm), 0>,
2723+
GPR_32;
2724+
26962725
def : MipsInstAlias<
26972726
"sgt $rd, $rs, $rt",
26982727
(SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;

‎llvm/test/MC/Mips/macro-sge.s‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
3+
4+
sge $4, $5
5+
# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
7+
sge $4, $5, $6
8+
# CHECK: slt $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x2a]
9+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
10+
sge $4, 16
11+
# CHECK: slti $4, $4, 16 # encoding: [0x28,0x84,0x00,0x10]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
13+
sge $4, $5, 16
14+
# CHECK: slti $4, $5, 16 # encoding: [0x28,0xa4,0x00,0x10]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
16+
sge $4, $5, 0x10000
17+
# CHECK: lui $4, 1 # encoding: [0x3c,0x04,0x00,0x01]
18+
# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
19+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
20+
sgeu $4, $5
21+
# CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
22+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
23+
sgeu $4, $5, $6
24+
# CHECK: sltu $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x2b]
25+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
26+
sgeu $4, 16
27+
# CHECK: sltiu $4, $4, 16 # encoding: [0x2c,0x84,0x00,0x10]
28+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
29+
sgeu $4, $5, 16
30+
# CHECK: sltiu $4, $5, 16 # encoding: [0x2c,0xa4,0x00,0x10]
31+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
32+
sgeu $4, $5, 0x10000
33+
# CHECK: lui $4, 1 # encoding: [0x3c,0x04,0x00,0x01]
34+
# CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
35+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
36+
sge $4, 0x10000
37+
# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
38+
# CHECK: slt $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2a]
39+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
40+
sgeu $4, 0x10000
41+
# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
42+
# CHECK: sltu $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2b]
43+
# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]

‎llvm/test/MC/Mips/macro-sge64.s‎

Lines changed: 29 additions & 0 deletions
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@@ -0,0 +1,29 @@
1+
# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
2+
# RUN: | FileCheck --check-prefix=MIPS32 %s
3+
# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
4+
# RUN: | FileCheck --check-prefix=MIPS64 %s
5+
6+
sge $4, $5, 0x100000000
7+
# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8+
# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
9+
# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
10+
# MIPS64: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
11+
# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
12+
sgeu $4, $5, 0x100000000
13+
# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14+
# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
15+
# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
16+
# MIPS64: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
17+
# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
18+
sge $4, 0x100000000
19+
# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20+
# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
21+
# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
22+
# MIPS64: slt $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2a]
23+
# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
24+
sgeu $4, 0x100000000
25+
# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26+
# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
27+
# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
28+
# MIPS64: sltu $4, $4, $1 # encoding: [0x00,0x81,0x20,0x2b]
29+
# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]

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