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lukel97lukel97
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[DAGCombiner] Combine vp.strided.store with unit stride to vp.store (#66774)
This is the VP equivalent of #66677. If we have a strided store where the stride is equal to the element width, we can just use a regular VP store.
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3 files changed

+174
-14
lines changed

3 files changed

+174
-14
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -540,6 +540,7 @@ namespace {
540540
SDValue visitVPGATHER(SDNode *N);
541541
SDValue visitVPSCATTER(SDNode *N);
542542
SDValue visitVP_STRIDED_LOAD(SDNode *N);
543+
SDValue visitVP_STRIDED_STORE(SDNode *N);
543544
SDValue visitFP_TO_FP16(SDNode *N);
544545
SDValue visitFP16_TO_FP(SDNode *N);
545546
SDValue visitFP_TO_BF16(SDNode *N);
@@ -11873,6 +11874,21 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
1187311874
return SDValue();
1187411875
}
1187511876

11877+
SDValue DAGCombiner::visitVP_STRIDED_STORE(SDNode *N) {
11878+
auto *SST = cast<VPStridedStoreSDNode>(N);
11879+
EVT EltVT = SST->getValue().getValueType().getVectorElementType();
11880+
// Combine strided stores with unit-stride to a regular VP store.
11881+
if (auto *CStride = dyn_cast<ConstantSDNode>(SST->getStride());
11882+
CStride && CStride->getZExtValue() == EltVT.getStoreSize()) {
11883+
return DAG.getStoreVP(SST->getChain(), SDLoc(N), SST->getValue(),
11884+
SST->getBasePtr(), SST->getOffset(), SST->getMask(),
11885+
SST->getVectorLength(), SST->getMemoryVT(),
11886+
SST->getMemOperand(), SST->getAddressingMode(),
11887+
SST->isTruncatingStore(), SST->isCompressingStore());
11888+
}
11889+
return SDValue();
11890+
}
11891+
1187611892
SDValue DAGCombiner::visitVPGATHER(SDNode *N) {
1187711893
VPGatherSDNode *MGT = cast<VPGatherSDNode>(N);
1187811894
SDValue Mask = MGT->getMask();
@@ -25997,6 +26013,10 @@ SDValue DAGCombiner::visitVPOp(SDNode *N) {
2599726013
if (SDValue SD = visitVP_STRIDED_LOAD(N))
2599826014
return SD;
2599926015

26016+
if (N->getOpcode() == ISD::EXPERIMENTAL_VP_STRIDED_STORE)
26017+
if (SDValue SD = visitVP_STRIDED_STORE(N))
26018+
return SD;
26019+
2600026020
// VP operations in which all vector elements are disabled - either by
2600126021
// determining that the mask is all false or that the EVL is 0 - can be
2600226022
// eliminated.

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll

Lines changed: 74 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,16 @@ define void @strided_vpstore_v8i8(<8 x i8> %val, ptr %ptr, i32 signext %stride,
8484
ret void
8585
}
8686

87+
define void @strided_vpstore_v8i8_unit_stride(<8 x i8> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
88+
; CHECK-LABEL: strided_vpstore_v8i8_unit_stride:
89+
; CHECK: # %bb.0:
90+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
91+
; CHECK-NEXT: vse8.v v8, (a0), v0.t
92+
; CHECK-NEXT: ret
93+
call void @llvm.experimental.vp.strided.store.v8i8.p0.i32(<8 x i8> %val, ptr %ptr, i32 1, <8 x i1> %m, i32 %evl)
94+
ret void
95+
}
96+
8797
declare void @llvm.experimental.vp.strided.store.v2i16.p0.i32(<2 x i16>, ptr, i32, <2 x i1>, i32)
8898

8999
define void @strided_vpstore_v2i16(<2 x i16> %val, ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
@@ -120,6 +130,16 @@ define void @strided_vpstore_v8i16(<8 x i16> %val, ptr %ptr, i32 signext %stride
120130
ret void
121131
}
122132

133+
define void @strided_vpstore_v8i16_unit_stride(<8 x i16> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
134+
; CHECK-LABEL: strided_vpstore_v8i16_unit_stride:
135+
; CHECK: # %bb.0:
136+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
137+
; CHECK-NEXT: vse16.v v8, (a0), v0.t
138+
; CHECK-NEXT: ret
139+
call void @llvm.experimental.vp.strided.store.v8i16.p0.i32(<8 x i16> %val, ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)
140+
ret void
141+
}
142+
123143
declare void @llvm.experimental.vp.strided.store.v2i32.p0.i32(<2 x i32>, ptr, i32, <2 x i1>, i32)
124144

125145
define void @strided_vpstore_v2i32(<2 x i32> %val, ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
@@ -144,6 +164,16 @@ define void @strided_vpstore_v4i32(<4 x i32> %val, ptr %ptr, i32 signext %stride
144164
ret void
145165
}
146166

167+
define void @strided_vpstore_v4i32_unit_stride(<4 x i32> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
168+
; CHECK-LABEL: strided_vpstore_v4i32_unit_stride:
169+
; CHECK: # %bb.0:
170+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
171+
; CHECK-NEXT: vse32.v v8, (a0), v0.t
172+
; CHECK-NEXT: ret
173+
call void @llvm.experimental.vp.strided.store.v4i32.p0.i32(<4 x i32> %val, ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)
174+
ret void
175+
}
176+
147177
declare void @llvm.experimental.vp.strided.store.v8i32.p0.i32(<8 x i32>, ptr, i32, <8 x i1>, i32)
148178

149179
define void @strided_vpstore_v8i32(<8 x i32> %val, ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
@@ -168,6 +198,16 @@ define void @strided_vpstore_v2i64(<2 x i64> %val, ptr %ptr, i32 signext %stride
168198
ret void
169199
}
170200

201+
define void @strided_vpstore_v2i64_unit_stride(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
202+
; CHECK-LABEL: strided_vpstore_v2i64_unit_stride:
203+
; CHECK: # %bb.0:
204+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
205+
; CHECK-NEXT: vse64.v v8, (a0), v0.t
206+
; CHECK-NEXT: ret
207+
call void @llvm.experimental.vp.strided.store.v2i64.p0.i32(<2 x i64> %val, ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)
208+
ret void
209+
}
210+
171211
declare void @llvm.experimental.vp.strided.store.v4i64.p0.i32(<4 x i64>, ptr, i32, <4 x i1>, i32)
172212

173213
define void @strided_vpstore_v4i64(<4 x i64> %val, ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
@@ -228,6 +268,16 @@ define void @strided_vpstore_v8f16(<8 x half> %val, ptr %ptr, i32 signext %strid
228268
ret void
229269
}
230270

271+
define void @strided_vpstore_v8f16_unit_stride(<8 x half> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
272+
; CHECK-LABEL: strided_vpstore_v8f16_unit_stride:
273+
; CHECK: # %bb.0:
274+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
275+
; CHECK-NEXT: vse16.v v8, (a0), v0.t
276+
; CHECK-NEXT: ret
277+
call void @llvm.experimental.vp.strided.store.v8f16.p0.i32(<8 x half> %val, ptr %ptr, i32 2, <8 x i1> %m, i32 %evl)
278+
ret void
279+
}
280+
231281
declare void @llvm.experimental.vp.strided.store.v2f32.p0.i32(<2 x float>, ptr, i32, <2 x i1>, i32)
232282

233283
define void @strided_vpstore_v2f32(<2 x float> %val, ptr %ptr, i32 signext %stride, <2 x i1> %m, i32 zeroext %evl) {
@@ -252,6 +302,16 @@ define void @strided_vpstore_v4f32(<4 x float> %val, ptr %ptr, i32 signext %stri
252302
ret void
253303
}
254304

305+
define void @strided_vpstore_v4f32_unit_stride(<4 x float> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
306+
; CHECK-LABEL: strided_vpstore_v4f32_unit_stride:
307+
; CHECK: # %bb.0:
308+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
309+
; CHECK-NEXT: vse32.v v8, (a0), v0.t
310+
; CHECK-NEXT: ret
311+
call void @llvm.experimental.vp.strided.store.v4f32.p0.i32(<4 x float> %val, ptr %ptr, i32 4, <4 x i1> %m, i32 %evl)
312+
ret void
313+
}
314+
255315
declare void @llvm.experimental.vp.strided.store.v8f32.p0.i32(<8 x float>, ptr, i32, <8 x i1>, i32)
256316

257317
define void @strided_vpstore_v8f32(<8 x float> %val, ptr %ptr, i32 signext %stride, <8 x i1> %m, i32 zeroext %evl) {
@@ -276,6 +336,16 @@ define void @strided_vpstore_v2f64(<2 x double> %val, ptr %ptr, i32 signext %str
276336
ret void
277337
}
278338

339+
define void @strided_vpstore_v2f64_unit_stride(<2 x double> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
340+
; CHECK-LABEL: strided_vpstore_v2f64_unit_stride:
341+
; CHECK: # %bb.0:
342+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
343+
; CHECK-NEXT: vse64.v v8, (a0), v0.t
344+
; CHECK-NEXT: ret
345+
call void @llvm.experimental.vp.strided.store.v2f64.p0.i32(<2 x double> %val, ptr %ptr, i32 8, <2 x i1> %m, i32 %evl)
346+
ret void
347+
}
348+
279349
declare void @llvm.experimental.vp.strided.store.v4f64.p0.i32(<4 x double>, ptr, i32, <4 x i1>, i32)
280350

281351
define void @strided_vpstore_v4f64(<4 x double> %val, ptr %ptr, i32 signext %stride, <4 x i1> %m, i32 zeroext %evl) {
@@ -343,10 +413,10 @@ define void @strided_store_v32f64(<32 x double> %v, ptr %ptr, i32 signext %strid
343413
; CHECK: # %bb.0:
344414
; CHECK-NEXT: li a4, 16
345415
; CHECK-NEXT: mv a3, a2
346-
; CHECK-NEXT: bltu a2, a4, .LBB27_2
416+
; CHECK-NEXT: bltu a2, a4, .LBB34_2
347417
; CHECK-NEXT: # %bb.1:
348418
; CHECK-NEXT: li a3, 16
349-
; CHECK-NEXT: .LBB27_2:
419+
; CHECK-NEXT: .LBB34_2:
350420
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
351421
; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
352422
; CHECK-NEXT: mul a3, a3, a1
@@ -369,10 +439,10 @@ define void @strided_store_v32f64_allones_mask(<32 x double> %v, ptr %ptr, i32 s
369439
; CHECK: # %bb.0:
370440
; CHECK-NEXT: li a4, 16
371441
; CHECK-NEXT: mv a3, a2
372-
; CHECK-NEXT: bltu a2, a4, .LBB28_2
442+
; CHECK-NEXT: bltu a2, a4, .LBB35_2
373443
; CHECK-NEXT: # %bb.1:
374444
; CHECK-NEXT: li a3, 16
375-
; CHECK-NEXT: .LBB28_2:
445+
; CHECK-NEXT: .LBB35_2:
376446
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
377447
; CHECK-NEXT: vsse64.v v8, (a0), a1
378448
; CHECK-NEXT: mul a3, a3, a1

‎llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

Lines changed: 80 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,16 @@ define void @strided_vpstore_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr, i32 signex
9696
ret void
9797
}
9898

99+
define void @strided_vpstore_nxv8i8_unit_stride(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
100+
; CHECK-LABEL: strided_vpstore_nxv8i8_unit_stride:
101+
; CHECK: # %bb.0:
102+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
103+
; CHECK-NEXT: vse8.v v8, (a0), v0.t
104+
; CHECK-NEXT: ret
105+
call void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8> %val, ptr %ptr, i32 1, <vscale x 8 x i1> %m, i32 %evl)
106+
ret void
107+
}
108+
99109
declare void @llvm.experimental.vp.strided.store.nxv1i16.p0.i32(<vscale x 1 x i16>, ptr, i32, <vscale x 1 x i1>, i32)
100110

101111
define void @strided_vpstore_nxv1i16(<vscale x 1 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
@@ -132,6 +142,16 @@ define void @strided_vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, i32 sign
132142
ret void
133143
}
134144

145+
define void @strided_vpstore_nxv4i16_unit_stride(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
146+
; CHECK-LABEL: strided_vpstore_nxv4i16_unit_stride:
147+
; CHECK: # %bb.0:
148+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
149+
; CHECK-NEXT: vse16.v v8, (a0), v0.t
150+
; CHECK-NEXT: ret
151+
call void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
152+
ret void
153+
}
154+
135155
declare void @llvm.experimental.vp.strided.store.nxv8i16.p0.i32(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>, i32)
136156

137157
define void @strided_vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -180,6 +200,16 @@ define void @strided_vpstore_nxv4i32(<vscale x 4 x i32> %val, ptr %ptr, i32 sign
180200
ret void
181201
}
182202

203+
define void @strided_vpstore_nxv4i32_unit_stride(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
204+
; CHECK-LABEL: strided_vpstore_nxv4i32_unit_stride:
205+
; CHECK: # %bb.0:
206+
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
207+
; CHECK-NEXT: vse32.v v8, (a0), v0.t
208+
; CHECK-NEXT: ret
209+
call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)
210+
ret void
211+
}
212+
183213
declare void @llvm.experimental.vp.strided.store.nxv8i32.p0.i32(<vscale x 8 x i32>, ptr, i32, <vscale x 8 x i1>, i32)
184214

185215
define void @strided_vpstore_nxv8i32(<vscale x 8 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -204,6 +234,16 @@ define void @strided_vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, i32 sign
204234
ret void
205235
}
206236

237+
define void @strided_vpstore_nxv1i64_unit_stride(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
238+
; CHECK-LABEL: strided_vpstore_nxv1i64_unit_stride:
239+
; CHECK: # %bb.0:
240+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
241+
; CHECK-NEXT: vse64.v v8, (a0), v0.t
242+
; CHECK-NEXT: ret
243+
call void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
244+
ret void
245+
}
246+
207247
declare void @llvm.experimental.vp.strided.store.nxv2i64.p0.i32(<vscale x 2 x i64>, ptr, i32, <vscale x 2 x i1>, i32)
208248

209249
define void @strided_vpstore_nxv2i64(<vscale x 2 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
@@ -276,6 +316,16 @@ define void @strided_vpstore_nxv4f16(<vscale x 4 x half> %val, ptr %ptr, i32 sig
276316
ret void
277317
}
278318

319+
define void @strided_vpstore_nxv4f16_unit_stride(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
320+
; CHECK-LABEL: strided_vpstore_nxv4f16_unit_stride:
321+
; CHECK: # %bb.0:
322+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
323+
; CHECK-NEXT: vse16.v v8, (a0), v0.t
324+
; CHECK-NEXT: ret
325+
call void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
326+
ret void
327+
}
328+
279329
declare void @llvm.experimental.vp.strided.store.nxv8f16.p0.i32(<vscale x 8 x half>, ptr, i32, <vscale x 8 x i1>, i32)
280330

281331
define void @strided_vpstore_nxv8f16(<vscale x 8 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -324,6 +374,16 @@ define void @strided_vpstore_nxv4f32(<vscale x 4 x float> %val, ptr %ptr, i32 si
324374
ret void
325375
}
326376

377+
define void @strided_vpstore_nxv4f32_unit_stride(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
378+
; CHECK-LABEL: strided_vpstore_nxv4f32_unit_stride:
379+
; CHECK: # %bb.0:
380+
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
381+
; CHECK-NEXT: vse32.v v8, (a0), v0.t
382+
; CHECK-NEXT: ret
383+
call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)
384+
ret void
385+
}
386+
327387
declare void @llvm.experimental.vp.strided.store.nxv8f32.p0.i32(<vscale x 8 x float>, ptr, i32, <vscale x 8 x i1>, i32)
328388

329389
define void @strided_vpstore_nxv8f32(<vscale x 8 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -348,6 +408,16 @@ define void @strided_vpstore_nxv1f64(<vscale x 1 x double> %val, ptr %ptr, i32 s
348408
ret void
349409
}
350410

411+
define void @strided_vpstore_nxv1f64_unit_stride(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
412+
; CHECK-LABEL: strided_vpstore_nxv1f64_unit_stride:
413+
; CHECK: # %bb.0:
414+
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
415+
; CHECK-NEXT: vse64.v v8, (a0), v0.t
416+
; CHECK-NEXT: ret
417+
call void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
418+
ret void
419+
}
420+
351421
declare void @llvm.experimental.vp.strided.store.nxv2f64.p0.i32(<vscale x 2 x double>, ptr, i32, <vscale x 2 x i1>, i32)
352422

353423
define void @strided_vpstore_nxv2f64(<vscale x 2 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
@@ -427,10 +497,10 @@ define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 sig
427497
; CHECK: # %bb.0:
428498
; CHECK-NEXT: csrr a3, vlenb
429499
; CHECK-NEXT: mv a4, a2
430-
; CHECK-NEXT: bltu a2, a3, .LBB34_2
500+
; CHECK-NEXT: bltu a2, a3, .LBB41_2
431501
; CHECK-NEXT: # %bb.1:
432502
; CHECK-NEXT: mv a4, a3
433-
; CHECK-NEXT: .LBB34_2:
503+
; CHECK-NEXT: .LBB41_2:
434504
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
435505
; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
436506
; CHECK-NEXT: sub a5, a2, a3
@@ -454,10 +524,10 @@ define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr
454524
; CHECK: # %bb.0:
455525
; CHECK-NEXT: csrr a3, vlenb
456526
; CHECK-NEXT: mv a4, a2
457-
; CHECK-NEXT: bltu a2, a3, .LBB35_2
527+
; CHECK-NEXT: bltu a2, a3, .LBB42_2
458528
; CHECK-NEXT: # %bb.1:
459529
; CHECK-NEXT: mv a4, a3
460-
; CHECK-NEXT: .LBB35_2:
530+
; CHECK-NEXT: .LBB42_2:
461531
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
462532
; CHECK-NEXT: vsse64.v v8, (a0), a1
463533
; CHECK-NEXT: sub a3, a2, a3
@@ -485,15 +555,15 @@ define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 sig
485555
; CHECK-NEXT: slli a6, a4, 1
486556
; CHECK-NEXT: vmv1r.v v24, v0
487557
; CHECK-NEXT: mv a5, a3
488-
; CHECK-NEXT: bltu a3, a6, .LBB36_2
558+
; CHECK-NEXT: bltu a3, a6, .LBB43_2
489559
; CHECK-NEXT: # %bb.1:
490560
; CHECK-NEXT: mv a5, a6
491-
; CHECK-NEXT: .LBB36_2:
561+
; CHECK-NEXT: .LBB43_2:
492562
; CHECK-NEXT: mv a7, a5
493-
; CHECK-NEXT: bltu a5, a4, .LBB36_4
563+
; CHECK-NEXT: bltu a5, a4, .LBB43_4
494564
; CHECK-NEXT: # %bb.3:
495565
; CHECK-NEXT: mv a7, a4
496-
; CHECK-NEXT: .LBB36_4:
566+
; CHECK-NEXT: .LBB43_4:
497567
; CHECK-NEXT: addi sp, sp, -16
498568
; CHECK-NEXT: .cfi_def_cfa_offset 16
499569
; CHECK-NEXT: csrr t0, vlenb
@@ -521,10 +591,10 @@ define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 sig
521591
; CHECK-NEXT: addi a3, a3, -1
522592
; CHECK-NEXT: and a0, a3, a0
523593
; CHECK-NEXT: vsse64.v v16, (a7), a2, v0.t
524-
; CHECK-NEXT: bltu a0, a4, .LBB36_6
594+
; CHECK-NEXT: bltu a0, a4, .LBB43_6
525595
; CHECK-NEXT: # %bb.5:
526596
; CHECK-NEXT: mv a0, a4
527-
; CHECK-NEXT: .LBB36_6:
597+
; CHECK-NEXT: .LBB43_6:
528598
; CHECK-NEXT: mul a3, a5, a2
529599
; CHECK-NEXT: add a1, a1, a3
530600
; CHECK-NEXT: srli a4, a4, 2

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