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ChunyuLiaoChunyuLiao
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Add smcntrpmf extension
spec: https://github.com/riscvarchive/riscv-smcntrpmf
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‎clang/test/Driver/print-supported-extensions-riscv.c

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Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@
123123
// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
124124
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
125125
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
126+
// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and instret privilege mode mode filtering)
126127
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
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// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
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// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)

‎clang/test/Preprocessor/riscv-target-features.c

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Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
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// CHECK-NOT: __riscv_shvstvecd {{.*$}}
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// CHECK-NOT: __riscv_smaia {{.*$}}
3131
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
32+
// CHECK-NOT: __riscv_smcntrpmf {{.*$}}
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// CHECK-NOT: __riscv_smcsrind {{.*$}}
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// CHECK-NOT: __riscv_smdbltrp {{.*$}}
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// CHECK-NOT: __riscv_smepmp {{.*$}}
@@ -1453,6 +1454,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
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// CHECK-SMCSRIND-EXT: __riscv_smcsrind 1000000{{$}}
14551456

1457+
// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismcntrpmf1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64ismcntrpmf1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
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// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32isscsrind1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -128,6 +128,7 @@ on support follow.
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``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Smaia`` Supported
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``Smcdeleg`` Supported
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``Smcntrpmf`` Supported
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``Smcsrind`` Supported
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``Smdbltrp`` Supported
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``Smepmp`` Supported

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -183,6 +183,8 @@ def FeatureStdExtZilsd
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def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,
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AssemblerPredicate<(all_of FeatureStdExtZilsd),
185185
"'Zilsd' (Load/Store pair instructions)">;
186+
def FeatureStdExtSmcntrpmf
187+
: RISCVExtension<1, 0, "Cycle and instret privilege mode mode filtering">;
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// Multiply Extensions
188190

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

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Original file line numberDiff line numberDiff line change
@@ -482,6 +482,14 @@ def : SysReg<"sctrdepth", 0x15f>;
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def : SysReg<"vsctrctl", 0x24e>;
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def : SysReg<"mctrctl", 0x34e>;
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485+
//===-----------------------------------------------
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// Cycle and Instret privilege mode filtering (Smcntrpmf)
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//===-----------------------------------------------
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def : SysReg<"mcyclecfg", 0x321>;
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def : SysReg<"minstretcfg", 0x322>;
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def : SysReg<"mcyclecfgh", 0x721>;
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def : SysReg<"minstretcfgh", 0x722>;
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//===-----------------------------------------------
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// Vendor CSRs
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//===-----------------------------------------------

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -147,6 +147,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
150+
; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s
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; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -301,6 +302,7 @@
301302
; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
302303
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s
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; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
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; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -485,6 +487,7 @@
485487
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
486488
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
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; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
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; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
488491
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
489492
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
490493
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -636,6 +639,7 @@
636639
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
637640
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
638641
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
642+
; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
639643
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
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; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
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; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"

‎llvm/test/CodeGen/RISCV/features-info.ll

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@@ -129,6 +129,7 @@
129129
; CHECK-NEXT: sifive7 - SiFive 7-Series processors.
130130
; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).
131131
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
132+
; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and instret privilege mode mode filtering).
132133
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
133134
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
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; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).

‎llvm/test/MC/RISCV/attribute-arch.s

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@@ -336,6 +336,9 @@
336336
.attribute arch, "rv32i_smcdeleg1p0"
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# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
338338

339+
.attribute arch, "rv32i_smcntrpmf1p0"
340+
# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"
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339342
.attribute arch, "rv32i_smepmp1p0"
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# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
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‎llvm/test/MC/RISCV/user-csr-names.s

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@@ -480,3 +480,51 @@ csrrs t2, 0xC1E, zero
480480
csrrs t1, hpmcounter31, zero
481481
# uimm12
482482
csrrs t2, 0xC1F, zero
483+
484+
# mcyclecfg
485+
# name
486+
# CHECK-INST: csrrs t1, mcyclecfg, zero
487+
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x32]
488+
# CHECK-INST-ALIAS: csrr t1, mcyclecfg
489+
csrrs t1, mcyclecfg, zero
490+
# uimm12
491+
# CHECK-INST: csrrs t2, mcyclecfg, zero
492+
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x32]
493+
# CHECK-INST-ALIAS: csrr t2, mcyclecfg
494+
csrrs t2, 0x321, zero
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496+
# minstretcfg
497+
# name
498+
# CHECK-INST: csrrs t1, minstretcfg, zero
499+
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x32]
500+
# CHECK-INST-ALIAS: csrr t1, minstretcfg
501+
csrrs t1, minstretcfg, zero
502+
# uimm12
503+
# CHECK-INST: csrrs t2, minstretcfg, zero
504+
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x32]
505+
# CHECK-INST-ALIAS: csrr t2, minstretcfg
506+
csrrs t2, 0x322, zero
507+
508+
# mcyclecfgh
509+
# name
510+
# CHECK-INST: csrrs t1, mcyclecfgh, zero
511+
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x72]
512+
# CHECK-INST-ALIAS: csrr t1, mcyclecfgh
513+
csrrs t1, mcyclecfgh, zero
514+
# uimm12
515+
# CHECK-INST: csrrs t2, mcyclecfgh, zero
516+
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x72]
517+
# CHECK-INST-ALIAS: csrr t2, mcyclecfgh
518+
csrrs t2, 0x721, zero
519+
520+
# minstretcfgh
521+
# name
522+
# CHECK-INST: csrrs t1, minstretcfgh, zero
523+
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x72]
524+
# CHECK-INST-ALIAS: csrr t1, minstretcfgh
525+
csrrs t1, minstretcfgh, zero
526+
# uimm12
527+
# CHECK-INST: csrrs t2, minstretcfgh, zero
528+
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x72]
529+
# CHECK-INST-ALIAS: csrr t2, minstretcfgh
530+
csrrs t2, 0x722, zero

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1076,6 +1076,7 @@ R"(All available -march extensions for RISC-V
10761076
shvstvecd 1.0
10771077
smaia 1.0
10781078
smcdeleg 1.0
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smcntrpmf 1.0
10791080
smcsrind 1.0
10801081
smdbltrp 1.0
10811082
smepmp 1.0

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