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Rohit AggarwalRohit Aggarwal
Rohit Aggarwal
authored and
Rohit Aggarwal
committed
Remove redundant pseudo mov instruction
1 parent 4f107cd commit 214caf4

33 files changed

+183
-285
lines changed

‎llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,11 +186,13 @@ static bool isCandidate(const MachineInstr *MI, Register &DefedReg,
186186
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187187
const MachineOperand &MO = MI->getOperand(i);
188188
if (MO.isReg()) {
189-
if (MO.isDef()) {
189+
if (MO.isDef() && DefedReg == MCRegister::NoRegister) {
190190
if (i == 0 && !MO.isImplicit() && !MO.isDead())
191191
DefedReg = MO.getReg();
192192
else
193193
return false;
194+
} else if (MI->isPseudo() && MI->isMoveImmediate()) {
195+
return DefedReg.isValid();
194196
} else if (MO.getReg() && MO.getReg() != FrameReg)
195197
return false;
196198
} else if (!(MO.isImm() || MO.isCImm() || MO.isFPImm() || MO.isCPI() ||

‎llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,6 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
8080
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
8181
; CHECK-NEXT: mov x0, xzr
8282
; CHECK-NEXT: mov x1, xzr
83-
; CHECK-NEXT: mov w8, #1 ; =0x1
8483
; CHECK-NEXT: stp xzr, xzr, [sp]
8584
; CHECK-NEXT: stp x8, xzr, [sp, #16]
8685
; CHECK-NEXT: bl _fprintf

‎llvm/test/CodeGen/AMDGPU/call-waitcnt.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ define amdgpu_kernel void @call_memory_no_dep(ptr addrspace(1) %ptr, i32) #0 {
4141
; GCN-NEXT: s_waitcnt lgkmcnt(0)
4242
; GCN-NEXT: global_store_dword v0, v0, s[6:7]
4343
; GCN-NEXT: s_mov_b64 s[6:7], s[4:5]
44-
; GCN-NEXT: v_mov_b32_e32 v0, 0
4544
; GCN-NEXT: s_mov_b32 s32, 0
4645
; GCN-NEXT: s_swappc_b64 s[30:31], s[8:9]
4746
; GCN-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/captured-frame-index.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,8 +113,7 @@ define amdgpu_kernel void @stored_fi_to_fi() #0 {
113113

114114
; GCN-LABEL: {{^}}stored_fi_to_global:
115115
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
116-
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
117-
; GCN: buffer_store_dword [[FI]]
116+
; GCN: buffer_store_dword v{{[0-9]+}}
118117
define amdgpu_kernel void @stored_fi_to_global(ptr addrspace(1) %ptr) #0 {
119118
%tmp = alloca float, addrspace(5)
120119
store float 0.0, ptr addrspace(5) %tmp

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,6 @@ define amdgpu_kernel void @test_sink_small_offset_global_atomic_csub_i32(ptr add
3131
; GCN-NEXT: v_cmpx_ne_u32_e32 0, v1
3232
; GCN-NEXT: s_cbranch_execz .LBB0_2
3333
; GCN-NEXT: ; %bb.1: ; %if
34-
; GCN-NEXT: v_mov_b32_e32 v0, 0
3534
; GCN-NEXT: v_mov_b32_e32 v1, 2
3635
; GCN-NEXT: s_waitcnt lgkmcnt(0)
3736
; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:28 glc

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ define amdgpu_kernel void @test_sink_small_offset_global_atomic_fadd_f32(ptr add
3333
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
3434
; GCN-NEXT: s_cbranch_execz .LBB0_2
3535
; GCN-NEXT: ; %bb.1: ; %if
36-
; GCN-NEXT: v_mov_b32_e32 v0, 0
3736
; GCN-NEXT: v_mov_b32_e32 v1, 2.0
3837
; GCN-NEXT: s_waitcnt lgkmcnt(0)
3938
; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28

‎llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,7 @@ done:
7272
; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:
7373
; GCN: s_and_saveexec_b64
7474
; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}
75-
; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
76-
; GFX9: global_load_sbyte {{v[0-9]+}}, [[ZERO]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
75+
; GFX9: global_load_sbyte {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
7776
; GCN: {{^}}.LBB2_2:
7877
; GCN: s_or_b64 exec
7978
define amdgpu_kernel void @test_sink_global_small_max_mubuf_offset(ptr addrspace(1) %out, ptr addrspace(1) %in) {

‎llvm/test/CodeGen/AMDGPU/div_v2i128.ll

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -323,8 +323,6 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
323323
; SDAG-NEXT: v_subrev_i32_e32 v36, vcc, 64, v30
324324
; SDAG-NEXT: v_lshr_b64 v[37:38], v[6:7], v30
325325
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v29
326-
; SDAG-NEXT: v_mov_b32_e32 v12, 0
327-
; SDAG-NEXT: v_mov_b32_e32 v13, 0
328326
; SDAG-NEXT: v_mov_b32_e32 v14, 0
329327
; SDAG-NEXT: v_mov_b32_e32 v15, 0
330328
; SDAG-NEXT: s_mov_b64 s[10:11], 0
@@ -1107,8 +1105,6 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
11071105
; SDAG-NEXT: v_subrev_i32_e32 v28, vcc, 64, v22
11081106
; SDAG-NEXT: v_lshr_b64 v[29:30], v[6:7], v22
11091107
; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v12
1110-
; SDAG-NEXT: v_mov_b32_e32 v20, 0
1111-
; SDAG-NEXT: v_mov_b32_e32 v21, 0
11121108
; SDAG-NEXT: v_mov_b32_e32 v10, 0
11131109
; SDAG-NEXT: v_mov_b32_e32 v11, 0
11141110
; SDAG-NEXT: s_mov_b64 s[10:11], 0
@@ -1679,8 +1675,6 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
16791675
; SDAG-NEXT: v_subrev_i32_e32 v37, vcc, 64, v32
16801676
; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v32
16811677
; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v31
1682-
; SDAG-NEXT: v_mov_b32_e32 v18, 0
1683-
; SDAG-NEXT: v_mov_b32_e32 v19, 0
16841678
; SDAG-NEXT: v_mov_b32_e32 v22, 0
16851679
; SDAG-NEXT: v_mov_b32_e32 v23, 0
16861680
; SDAG-NEXT: s_mov_b64 s[10:11], 0
@@ -1874,8 +1868,6 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
18741868
; SDAG-NEXT: v_subrev_i32_e32 v51, vcc, 64, v38
18751869
; SDAG-NEXT: v_lshr_b64 v[22:23], v[4:5], v38
18761870
; SDAG-NEXT: v_add_i32_e32 v50, vcc, -1, v37
1877-
; SDAG-NEXT: v_mov_b32_e32 v18, 0
1878-
; SDAG-NEXT: v_mov_b32_e32 v19, 0
18791871
; SDAG-NEXT: v_mov_b32_e32 v20, 0
18801872
; SDAG-NEXT: v_mov_b32_e32 v21, 0
18811873
; SDAG-NEXT: s_mov_b64 s[10:11], 0
@@ -2562,8 +2554,6 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
25622554
; SDAG-NEXT: v_subrev_i32_e32 v35, vcc, 64, v30
25632555
; SDAG-NEXT: v_lshr_b64 v[26:27], v[2:3], v30
25642556
; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v8
2565-
; SDAG-NEXT: v_mov_b32_e32 v20, 0
2566-
; SDAG-NEXT: v_mov_b32_e32 v21, 0
25672557
; SDAG-NEXT: v_mov_b32_e32 v24, 0
25682558
; SDAG-NEXT: v_mov_b32_e32 v25, 0
25692559
; SDAG-NEXT: s_mov_b64 s[10:11], 0
@@ -2737,8 +2727,6 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
27372727
; SDAG-NEXT: v_subrev_i32_e32 v39, vcc, 64, v34
27382728
; SDAG-NEXT: v_lshr_b64 v[26:27], v[6:7], v34
27392729
; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v12
2740-
; SDAG-NEXT: v_mov_b32_e32 v22, 0
2741-
; SDAG-NEXT: v_mov_b32_e32 v23, 0
27422730
; SDAG-NEXT: v_mov_b32_e32 v24, 0
27432731
; SDAG-NEXT: v_mov_b32_e32 v25, 0
27442732
; SDAG-NEXT: s_mov_b64 s[10:11], 0

‎llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,6 @@ define void @callee_with_stack_and_call() #0 {
5353
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
5454
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
5555
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
56-
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
5756
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
5857
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
5958
; NO-SPILL-TO-VGPR-NEXT: v_writelane_b32 v0, s31, 0
@@ -77,7 +76,6 @@ define void @callee_with_stack_and_call() #0 {
7776
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:16
7877
; NO-SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
7978
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
80-
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 s[4:5], exec
8179
; NO-SPILL-TO-VGPR-NEXT: s_mov_b64 exec, 1
8280
; NO-SPILL-TO-VGPR-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:16
8381
; NO-SPILL-TO-VGPR-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload

‎llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -3234,20 +3234,20 @@ define amdgpu_gfx void @call_72xi32() #1 {
32343234
; GFX11-NEXT: scratch_store_b128 off, v[0:3], s1
32353235
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v3, 0
32363236
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
3237-
; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, 0
3238-
; GFX11-NEXT: v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v6, 0
3239-
; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0
3240-
; GFX11-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, 0
3241-
; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
3242-
; GFX11-NEXT: v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v14, 0
3243-
; GFX11-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v16, 0
3244-
; GFX11-NEXT: v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v18, 0
3245-
; GFX11-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v20, 0
3246-
; GFX11-NEXT: v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v22, 0
3247-
; GFX11-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v24, 0
3248-
; GFX11-NEXT: v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v26, 0
3249-
; GFX11-NEXT: v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v28, 0
3250-
; GFX11-NEXT: v_dual_mov_b32 v31, 0 :: v_dual_mov_b32 v30, 0
3237+
; GFX11-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
3238+
; GFX11-NEXT: v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
3239+
; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
3240+
; GFX11-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
3241+
; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v14, 0
3242+
; GFX11-NEXT: v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v16, 0
3243+
; GFX11-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v18, 0
3244+
; GFX11-NEXT: v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v20, 0
3245+
; GFX11-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v22, 0
3246+
; GFX11-NEXT: v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v24, 0
3247+
; GFX11-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v26, 0
3248+
; GFX11-NEXT: v_dual_mov_b32 v27, 0 :: v_dual_mov_b32 v28, 0
3249+
; GFX11-NEXT: v_dual_mov_b32 v29, 0 :: v_dual_mov_b32 v30, 0
3250+
; GFX11-NEXT: v_mov_b32_e32 v31, 0
32513251
; GFX11-NEXT: s_mov_b32 s1, return_72xi32@abs32@hi
32523252
; GFX11-NEXT: s_mov_b32 s0, return_72xi32@abs32@lo
32533253
; GFX11-NEXT: v_writelane_b32 v60, s31, 1

‎llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -225,12 +225,10 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
225225
; MUBUF-NEXT: ; %bb.2: ; %split
226226
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000
227227
; MUBUF-NEXT: v_or_b32_e32 v0, 0x12d4, v1
228-
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000
229228
; MUBUF-NEXT: s_movk_i32 s4, 0x4000
230229
; MUBUF-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen glc
231230
; MUBUF-NEXT: s_waitcnt vmcnt(0)
232231
; MUBUF-NEXT: v_or_b32_e32 v0, 0x12d0, v1
233-
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000
234232
; MUBUF-NEXT: s_or_b32 s4, s4, 0x12c0
235233
; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen glc
236234
; MUBUF-NEXT: s_waitcnt vmcnt(0)

‎llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,6 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
395395
; GFX908-NEXT: buffer_load_dword v2, off, s[0:3], s33 offset:168
396396
; GFX908-NEXT: s_waitcnt vmcnt(0)
397397
; GFX908-NEXT: s_mov_b64 exec, s[16:17]
398-
; GFX908-NEXT: s_mov_b64 s[16:17], exec
399398
; GFX908-NEXT: s_mov_b64 exec, 1
400399
; GFX908-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:168
401400
; GFX908-NEXT: v_writelane_b32 v2, s31, 0
@@ -743,7 +742,6 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 {
743742
; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:168
744743
; GFX908-NEXT: s_waitcnt vmcnt(0)
745744
; GFX908-NEXT: s_mov_b64 exec, s[4:5]
746-
; GFX908-NEXT: s_mov_b64 s[4:5], exec
747745
; GFX908-NEXT: s_mov_b64 exec, 1
748746
; GFX908-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:168
749747
; GFX908-NEXT: buffer_load_dword v0, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload

‎llvm/test/CodeGen/AMDGPU/required-export-priority.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -267,7 +267,6 @@ define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 {
267267
; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
268268
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2)
269269
; GCN-NEXT: v_cndmask_b32_e32 v0, 16, v2, vcc_lo
270-
; GCN-NEXT: v_mov_b32_e32 v2, 0
271270
; GCN-NEXT: scratch_store_b32 v0, v1, off
272271
; GCN-NEXT: scratch_load_b32 v0, off, off
273272
; GCN-NEXT: v_mov_b32_e32 v1, 1.0

‎llvm/test/CodeGen/AMDGPU/sibling-call.ll

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -388,11 +388,7 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
388388
; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32_a32i32@gotpcrel32@lo+4
389389
; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32_a32i32@gotpcrel32@hi+12
390390
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
391-
; GCN-NEXT: v_mov_b32_e32 v2, 0
392391
; GCN-NEXT: v_writelane_b32 v40, s30, 0
393-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32
394-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4
395-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
396392
; GCN-NEXT: v_mov_b32_e32 v2, 0
397393
; GCN-NEXT: v_mov_b32_e32 v3, 0
398394
; GCN-NEXT: v_mov_b32_e32 v4, 0
@@ -423,6 +419,9 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
423419
; GCN-NEXT: v_mov_b32_e32 v29, 0
424420
; GCN-NEXT: v_mov_b32_e32 v30, 0
425421
; GCN-NEXT: v_writelane_b32 v40, s31, 1
422+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32
423+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4
424+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
426425
; GCN-NEXT: s_waitcnt lgkmcnt(0)
427426
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
428427
; GCN-NEXT: v_readlane_b32 s31, v40, 1
@@ -528,10 +527,6 @@ define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg
528527
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:48
529528
; GCN-NEXT: s_waitcnt vmcnt(0)
530529
; GCN-NEXT: v_mov_b32_e32 v2, 0
531-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32
532-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4
533-
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
534-
; GCN-NEXT: v_mov_b32_e32 v2, 0
535530
; GCN-NEXT: v_mov_b32_e32 v3, 0
536531
; GCN-NEXT: v_mov_b32_e32 v4, 0
537532
; GCN-NEXT: v_mov_b32_e32 v5, 0
@@ -560,6 +555,9 @@ define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg
560555
; GCN-NEXT: v_mov_b32_e32 v28, 0
561556
; GCN-NEXT: v_mov_b32_e32 v29, 0
562557
; GCN-NEXT: v_mov_b32_e32 v30, 0
558+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32
559+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:4
560+
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8
563561
; GCN-NEXT: s_waitcnt lgkmcnt(0)
564562
; GCN-NEXT: s_setpc_b64 s[4:5]
565563
entry:
@@ -928,7 +926,6 @@ define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64
928926
; GCN-NEXT: s_add_u32 s16, s16, void_fastcc_byval_and_stack_passed@rel32@lo+4
929927
; GCN-NEXT: s_addc_u32 s17, s17, void_fastcc_byval_and_stack_passed@rel32@hi+12
930928
; GCN-NEXT: v_mov_b32_e32 v0, 0
931-
; GCN-NEXT: v_mov_b32_e32 v1, 0
932929
; GCN-NEXT: v_mov_b32_e32 v2, 0
933930
; GCN-NEXT: v_mov_b32_e32 v3, 0
934931
; GCN-NEXT: v_mov_b32_e32 v4, 0

‎llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9971,7 +9971,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
99719971
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
99729972
; GFX6-NEXT: s_waitcnt vmcnt(0)
99739973
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
9974-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
99759974
; GFX6-NEXT: s_mov_b64 exec, 0xff
99769975
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
99779976
; GFX6-NEXT: s_mov_b32 s34, 0x80c00
@@ -9989,7 +9988,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
99899988
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
99909989
; GFX6-NEXT: s_waitcnt vmcnt(0)
99919990
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
9992-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
99939991
; GFX6-NEXT: s_mov_b64 exec, 0xff
99949992
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
99959993
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10007,7 +10005,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1000710005
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
1000810006
; GFX6-NEXT: s_waitcnt vmcnt(0)
1000910007
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
10010-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
1001110008
; GFX6-NEXT: s_mov_b64 exec, 0xff
1001210009
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1001310010
; GFX6-NEXT: s_mov_b32 s34, 0x81400
@@ -10025,7 +10022,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1002510022
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
1002610023
; GFX6-NEXT: s_waitcnt vmcnt(0)
1002710024
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
10028-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
1002910025
; GFX6-NEXT: s_mov_b64 exec, 0xff
1003010026
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1003110027
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10043,7 +10039,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1004310039
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
1004410040
; GFX6-NEXT: s_waitcnt vmcnt(0)
1004510041
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
10046-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
1004710042
; GFX6-NEXT: s_mov_b64 exec, 0xff
1004810043
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1004910044
; GFX6-NEXT: s_mov_b32 s34, 0x81c00
@@ -10061,7 +10056,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1006110056
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
1006210057
; GFX6-NEXT: s_waitcnt vmcnt(0)
1006310058
; GFX6-NEXT: s_mov_b64 exec, s[6:7]
10064-
; GFX6-NEXT: s_mov_b64 s[6:7], exec
1006510059
; GFX6-NEXT: s_mov_b64 exec, 15
1006610060
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1006710061
; GFX6-NEXT: s_waitcnt expcnt(0)
@@ -10105,7 +10099,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1010510099
; GFX6-NEXT: buffer_load_dword v4, off, s[40:43], 0
1010610100
; GFX6-NEXT: s_waitcnt vmcnt(0)
1010710101
; GFX6-NEXT: s_mov_b64 exec, s[34:35]
10108-
; GFX6-NEXT: s_mov_b64 s[34:35], exec
1010910102
; GFX6-NEXT: s_mov_b64 exec, 15
1011010103
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1011110104
; GFX6-NEXT: s_mov_b32 s44, 0x82c00
@@ -10165,7 +10158,6 @@ define amdgpu_kernel void @test_limited_sgpr(ptr addrspace(1) %out, ptr addrspac
1016510158
; GFX6-NEXT: s_waitcnt vmcnt(0)
1016610159
; GFX6-NEXT: s_mov_b64 exec, s[4:5]
1016710160
; GFX6-NEXT: s_mov_b64 s[36:37], s[0:1]
10168-
; GFX6-NEXT: s_mov_b64 s[4:5], exec
1016910161
; GFX6-NEXT: s_mov_b64 exec, 15
1017010162
; GFX6-NEXT: buffer_store_dword v4, off, s[40:43], 0
1017110163
; GFX6-NEXT: s_mov_b32 s6, 0x80800

‎llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,6 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt
3535
; CHECK-NEXT: andl $1, %ebp
3636
; CHECK-NEXT: xorpd %xmm0, %xmm0
3737
; CHECK-NEXT: xorl %eax, %eax
38-
; CHECK-NEXT: xorl %ecx, %ecx
3938
; CHECK-NEXT: xorpd %xmm1, %xmm1
4039
; CHECK-NEXT: .p2align 4
4140
; CHECK-NEXT: .LBB0_7: # %bb.i28.i

‎llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,6 @@ define dso_local void @test4(i16 signext %0, i16 signext %1) nounwind {
174174
; CHECK-NEXT: incl %edi
175175
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
176176
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
177-
; CHECK-NEXT: xorl %eax, %eax
178177
; CHECK-NEXT: testb %al, %al
179178
; CHECK-NEXT: jne .LBB3_4
180179
; CHECK-NEXT: .LBB3_2: # %amx2
@@ -190,7 +189,6 @@ define dso_local void @test4(i16 signext %0, i16 signext %1) nounwind {
190189
; CHECK-NEXT: decl %edi
191190
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
192191
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
193-
; CHECK-NEXT: xorl %eax, %eax
194192
; CHECK-NEXT: testb %al, %al
195193
; CHECK-NEXT: jne .LBB3_2
196194
; CHECK-NEXT: .LBB3_4: # %amx1

‎llvm/test/CodeGen/X86/avx-load-store.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,6 @@ define void @f_f() nounwind {
216216
; CHECK-NEXT: jne .LBB9_2
217217
; CHECK-NEXT: # %bb.1: # %cif_mask_all
218218
; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed
219-
; CHECK-NEXT: xorl %eax, %eax
220219
; CHECK-NEXT: testb %al, %al
221220
; CHECK-NEXT: jne .LBB9_4
222221
; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all

‎llvm/test/CodeGen/X86/avx512-i1test.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,13 @@ define void @func() {
1414
; CHECK-NEXT: retq
1515
; CHECK-NEXT: .p2align 4
1616
; CHECK-NEXT: .LBB0_1: # %bb33
17-
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
18-
; CHECK-NEXT: testb %al, %al
19-
; CHECK-NEXT: jne .LBB0_1
20-
; CHECK-NEXT: # %bb.2: # %bb35
21-
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
22-
; CHECK-NEXT: testb %al, %al
23-
; CHECK-NEXT: jmp .LBB0_1
17+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
18+
; CHECK-NEXT: testb %al, %al
19+
; CHECK-NEXT: jne .LBB0_1
20+
; CHECK-NEXT: # %bb.2: # %bb35
21+
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
22+
; CHECK-NEXT: testb %al, %al
23+
; CHECK-NEXT: jmp .LBB0_1
2424
bb1:
2525
br i1 poison, label %L_10, label %L_10
2626

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