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[X86][AMX] Add AMX FP8 new APIs (#115829)
This is a follow-up to #113850. Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
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-23
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‎clang/include/clang/Basic/BuiltinsX86_64.def

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,10 @@ TARGET_BUILTIN(__builtin_ia32_tcvtrowps2phl_internal, "V32xUsUsV256iUi", "n", "a
148148
TARGET_BUILTIN(__builtin_ia32_tilemovrow_internal, "V16iUsUsV256iUi", "n", "amx-avx512,avx10.2-512")
149149
TARGET_BUILTIN(__builtin_ia32_tmmultf32ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-tf32")
150150
TARGET_BUILTIN(__builtin_ia32_ttmmultf32ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-tf32,amx-transpose")
151+
TARGET_BUILTIN(__builtin_ia32_tdpbf8ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-fp8")
152+
TARGET_BUILTIN(__builtin_ia32_tdpbhf8ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-fp8")
153+
TARGET_BUILTIN(__builtin_ia32_tdphbf8ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-fp8")
154+
TARGET_BUILTIN(__builtin_ia32_tdphf8ps_internal, "V256iUsUsUsV256iV256iV256i", "n", "amx-fp8")
151155

152156
// AMX
153157
TARGET_BUILTIN(__builtin_ia32_tile_loadconfig, "vvC*", "n", "amx-tile")

‎clang/lib/Headers/amxfp8intrin.h

Lines changed: 156 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -15,81 +15,216 @@
1515
#define __AMXFP8INTRIN_H
1616
#ifdef __x86_64__
1717

18-
/// Peform the dot product of a BF8 value \a a by a BF8 value \a b accumulating
19-
/// into a Single Precision (FP32) source/dest \a dst.
18+
#define __DEFAULT_FN_ATTRS_FP8 \
19+
__attribute__((__always_inline__, __nodebug__, __target__("amx-fp8")))
20+
21+
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_FP8
22+
_tile_dpbf8ps_internal(unsigned short m, unsigned short n, unsigned short k,
23+
_tile1024i dst, _tile1024i src1, _tile1024i src2) {
24+
return __builtin_ia32_tdpbf8ps_internal(m, n, k, dst, src1, src2);
25+
}
26+
27+
/// Perform the dot product of a BF8 value \a src1 by a BF8 value \a src2
28+
/// accumulating into a Single Precision (FP32) source/dest \a dst.
2029
///
2130
/// \headerfile <immintrin.h>
2231
///
2332
/// \code
24-
/// void _tile_dpbf8ps (__tile dst, __tile a, __tile b)
33+
/// void __tile_dpbf8ps (__tile1024i *dst, __tile1024i src1, __tile1024i src2)
34+
/// \endcode
35+
///
36+
/// \code{.operation}
37+
/// FOR m := 0 TO dst.rows - 1
38+
/// temp1[(dst.colsb / 4 - 1) : 0] = 0
39+
/// FOR k := 0 TO src1.colsb / 4 - 1
40+
/// FOR n := 0 TO dst.colsb / 4 - 1
41+
/// temp1[n] +=
42+
/// INT64(src1.row[m].float8[4*k+0]) * INT64(src2.row[k].float8[4*n+0])
43+
/// + INT64(src1.row[m].float8[4*k+1]) * INT64(src2.row[k].float8[4*n+1])
44+
/// + INT64(src1.row[m].float8[4*k+2]) * INT64(src2.row[k].float8[4*n+2])
45+
/// + INT64(src1.row[m].float8[4*k+3]) * INT64(src2.row[k].float8[4*n+3])
46+
/// ENDFOR
47+
/// ENDFOR
48+
/// FOR n := 0 TO dst.colsb / 4 - 1
49+
/// tmp.row[m].fp32[n] = dst.row[m].fp32[n] + FP32(temp1[n])
50+
/// ENDFOR
51+
/// write_row_and_zero(dst, m, tmp, dst.colsb)
52+
/// zero_upper_rows(dst, dst.rows)
53+
/// zero_tileconfig_start()
2554
/// \endcode
2655
///
2756
/// This intrinsic corresponds to the \c TDPBF8PS instruction.
2857
///
2958
/// \param dst
3059
/// The destination tile. Max size is 1024 Bytes.
31-
/// \param a
60+
/// \param src1
3261
/// The 1st source tile. Max size is 1024 Bytes.
33-
/// \param b
62+
/// \param src2
3463
/// The 2nd source tile. Max size is 1024 Bytes.
35-
#define _tile_dpbf8ps(dst, a, b) __builtin_ia32_tdpbf8ps((dst), (a), (b))
64+
__DEFAULT_FN_ATTRS_FP8 static void
65+
__tile_dpbf8ps(__tile1024i *dst, __tile1024i src1, __tile1024i src2) {
66+
dst->tile = _tile_dpbf8ps_internal(src1.row, src2.col, src1.col, dst->tile,
67+
src1.tile, src2.tile);
68+
}
3669

37-
/// Perform the dot product of a BF8 value \a a by an HF8 value \a b
70+
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_FP8
71+
_tile_dpbhf8ps_internal(unsigned short m, unsigned short n, unsigned short k,
72+
_tile1024i dst, _tile1024i src1, _tile1024i src2) {
73+
return __builtin_ia32_tdpbhf8ps_internal(m, n, k, dst, src1, src2);
74+
}
75+
76+
/// Perform the dot product of a BF8 value \a src1 by an HF8 value \a src2
3877
/// accumulating into a Single Precision (FP32) source/dest \a dst.
3978
///
4079
/// \headerfile <immintrin.h>
4180
///
4281
/// \code
43-
/// void _tile_dpbhf8ps (__tile dst, __tile a, __tile b)
82+
/// void __tile_dpbhf8ps (__tile1024i dst, __tile1024i src1, __tile1024i src2)
83+
/// \endcode
84+
///
85+
/// \code{.operation}
86+
/// FOR m := 0 TO dst.rows - 1
87+
/// temp1[(dst.colsb / 4 - 1) : 0] = 0
88+
/// FOR k := 0 TO src1.colsb / 4 - 1
89+
/// FOR n := 0 TO dst.colsb / 4 - 1
90+
/// temp1[n] +=
91+
/// INT64(src1.row[m].float8[4*k+0]) * INT64(src2.row[k].float8[4*n+0])
92+
/// + INT64(src1.row[m].float8[4*k+1]) * INT64(src2.row[k].float8[4*n+1])
93+
/// + INT64(src1.row[m].float8[4*k+2]) * INT64(src2.row[k].float8[4*n+2])
94+
/// + INT64(src1.row[m].float8[4*k+3]) * INT64(src2.row[k].float8[4*n+3])
95+
/// ENDFOR
96+
/// ENDFOR
97+
/// FOR n := 0 TO dst.colsb / 4 - 1
98+
/// tmp.row[m].fp32[n] = dst.row[m].fp32[n] + FP32(temp1[n])
99+
/// ENDFOR
100+
/// write_row_and_zero(dst, m, tmp, dst.colsb)
101+
/// zero_upper_rows(dst, dst.rows)
102+
/// zero_tileconfig_start()
44103
/// \endcode
45104
///
46105
/// This intrinsic corresponds to the \c TDPBHF8PS instruction.
47106
///
48107
/// \param dst
49108
/// The destination tile. Max size is 1024 Bytes.
50-
/// \param a
109+
/// \param src1
51110
/// The 1st source tile. Max size is 1024 Bytes.
52-
/// \param b
111+
/// \param src2
53112
/// The 2nd source tile. Max size is 1024 Bytes.
54-
#define _tile_dpbhf8ps(dst, a, b) __builtin_ia32_tdpbhf8ps((dst), (a), (b))
113+
__DEFAULT_FN_ATTRS_FP8 static void
114+
__tile_dpbhf8ps(__tile1024i *dst, __tile1024i src1, __tile1024i src2) {
115+
dst->tile = _tile_dpbhf8ps_internal(src1.row, src2.col, src1.col, dst->tile,
116+
src1.tile, src2.tile);
117+
}
118+
119+
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_FP8
120+
_tile_dphbf8ps_internal(unsigned short m, unsigned short n, unsigned short k,
121+
_tile1024i dst, _tile1024i src1, _tile1024i src2) {
122+
return __builtin_ia32_tdphbf8ps_internal(m, n, k, dst, src1, src2);
123+
}
55124

56-
/// Perform the dot product of an HF8 value \a a by a BF8 value \a b
125+
/// Perform the dot product of an HF8 value \a src1 by a BF8 value \a src2
57126
/// accumulating into a Single Precision (FP32) source/dest \a dst.
58127
///
59128
/// \headerfile <immintrin.h>
60129
///
61130
/// \code
62-
/// void _tile_dphbf8ps (__tile dst, __tile a, __tile b)
131+
/// void __tile_dphbf8ps (__tile1024i dst, __tile1024i src1, __tile1024i src2)
132+
/// \endcode
133+
///
134+
/// \code{.operation}
135+
/// FOR m := 0 TO dst.rows - 1
136+
/// temp1[(dst.colsb / 4 - 1) : 0] = 0
137+
/// FOR k := 0 TO src1.colsb / 4 - 1
138+
/// FOR n := 0 TO dst.colsb / 4 - 1
139+
/// temp1[n] +=
140+
/// INT64(src1.row[m].float8[4*k+0]) * INT64(src2.row[k].float8[4*n+0])
141+
/// + INT64(src1.row[m].float8[4*k+1]) * INT64(src2.row[k].float8[4*n+1])
142+
/// + INT64(src1.row[m].float8[4*k+2]) * INT64(src2.row[k].float8[4*n+2])
143+
/// + INT64(src1.row[m].float8[4*k+3]) * INT64(src2.row[k].float8[4*n+3])
144+
/// ENDFOR
145+
/// ENDFOR
146+
/// FOR n := 0 TO dst.colsb / 4 - 1
147+
/// tmp.row[m].fp32[n] = dst.row[m].fp32[n] + FP32(temp1[n])
148+
/// ENDFOR
149+
/// write_row_and_zero(dst, m, tmp, dst.colsb)
150+
/// zero_upper_rows(dst, dst.rows)
151+
/// zero_tileconfig_start()
63152
/// \endcode
64153
///
65154
/// This intrinsic corresponds to the \c TDPHBF8PS instruction.
66155
///
67156
/// \param dst
68157
/// The destination tile. Max size is 1024 Bytes.
69-
/// \param a
158+
/// \param src1
70159
/// The 1st source tile. Max size is 1024 Bytes.
71-
/// \param b
160+
/// \param src2
72161
/// The 2nd source tile. Max size is 1024 Bytes.
73-
#define _tile_dphbf8ps(dst, a, b) __builtin_ia32_tdphbf8ps((dst), (a), (b))
74162

75-
/// Perform the dot product of an HF8 value \a a by an HF8 value \a b
163+
__DEFAULT_FN_ATTRS_FP8 static void
164+
__tile_dphbf8ps(__tile1024i *dst, __tile1024i src1, __tile1024i src2) {
165+
dst->tile = _tile_dphbf8ps_internal(src1.row, src2.col, src1.col, dst->tile,
166+
src1.tile, src2.tile);
167+
}
168+
169+
static __inline__ _tile1024i __DEFAULT_FN_ATTRS_FP8
170+
_tile_dphf8ps_internal(unsigned short m, unsigned short n, unsigned short k,
171+
_tile1024i dst, _tile1024i src1, _tile1024i src2) {
172+
return __builtin_ia32_tdphf8ps_internal(m, n, k, dst, src1, src2);
173+
}
174+
175+
/// Perform the dot product of an HF8 value \a src1 by an HF8 value \a src2
76176
/// accumulating into a Single Precision (FP32) source/dest \a dst.
77177
///
78178
/// \headerfile <immintrin.h>
79179
///
80180
/// \code
81-
/// void _tile_dphf8ps (__tile dst, __tile a, __tile b)
181+
/// void __tile_dphf8ps (__tile1024i dst, __tile1024i src1, __tile1024i src2)
182+
/// \endcode
183+
///
184+
/// \code{.operation}
185+
/// FOR m := 0 TO dst.rows - 1
186+
/// temp1[(dst.colsb / 4 - 1) : 0] = 0
187+
/// FOR k := 0 TO src1.colsb / 4 - 1
188+
/// FOR n := 0 TO dst.colsb / 4 - 1
189+
/// temp1[n] +=
190+
/// INT64(src1.row[m].float8[4*k+0]) * INT64(src2.row[k].float8[4*n+0])
191+
/// + INT64(src1.row[m].float8[4*k+1]) * INT64(src2.row[k].float8[4*n+1])
192+
/// + INT64(src1.row[m].float8[4*k+2]) * INT64(src2.row[k].float8[4*n+2])
193+
/// + INT64(src1.row[m].float8[4*k+3]) * INT64(src2.row[k].float8[4*n+3])
194+
/// ENDFOR
195+
/// ENDFOR
196+
/// FOR n := 0 TO dst.colsb / 4 - 1
197+
/// tmp.row[m].fp32[n] = dst.row[m].fp32[n] + FP32(temp1[n])
198+
/// ENDFOR
199+
/// write_row_and_zero(dst, m, tmp, dst.colsb)
200+
/// zero_upper_rows(dst, dst.rows)
201+
/// zero_tileconfig_start()
82202
/// \endcode
83203
///
84204
/// This intrinsic corresponds to the \c TDPHF8PS instruction.
85205
///
86206
/// \param dst
87207
/// The destination tile. Max size is 1024 Bytes.
88-
/// \param a
208+
/// \param src1
89209
/// The 1st source tile. Max size is 1024 Bytes.
90-
/// \param b
210+
/// \param src2
91211
/// The 2nd source tile. Max size is 1024 Bytes.
92-
#define _tile_dphf8ps(dst, a, b) __builtin_ia32_tdphf8ps((dst), (a), (b))
212+
__DEFAULT_FN_ATTRS_FP8 static void
213+
__tile_dphf8ps(__tile1024i *dst, __tile1024i src1, __tile1024i src2) {
214+
dst->tile = _tile_dphf8ps_internal(src1.row, src2.col, src1.col, dst->tile,
215+
src1.tile, src2.tile);
216+
}
217+
218+
#define _tile_dpbf8ps(dst, src1, src2) \
219+
__builtin_ia32_tdpbf8ps((dst), (src1), (src2))
220+
#define _tile_dpbhf8ps(dst, src1, src2) \
221+
__builtin_ia32_tdpbhf8ps((dst), (src1), (src2))
222+
#define _tile_dphbf8ps(dst, src1, src2) \
223+
__builtin_ia32_tdphbf8ps((dst), (src1), (src2))
224+
#define _tile_dphf8ps(dst, src1, src2) \
225+
__builtin_ia32_tdphf8ps((dst), (src1), (src2))
226+
227+
#undef __DEFAULT_FN_ATTRS_FP8
93228

94229
#endif /* __x86_64__ */
95230
#endif /* __AMXFP8INTRIN_H */

‎clang/test/CodeGen/X86/amx_fp8_api.c

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-fp8 \
2+
// RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s
3+
#include <immintrin.h>
4+
5+
void test_tdpbf8ps(__tile1024i src1, __tile1024i src2, __tile1024i dst) {
6+
//CHECK-LABEL: @test_tdpbf8ps
7+
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
8+
//CHECK-DAG: call x86_amx @llvm.x86.tdpbf8ps.internal
9+
//CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
10+
__tile_dpbf8ps(&dst, src1, src2);
11+
}
12+
13+
void test_tdpbhf8ps(__tile1024i src1, __tile1024i src2, __tile1024i dst) {
14+
//CHECK-LABEL: @test_tdpbhf8ps
15+
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
16+
//CHECK-DAG: call x86_amx @llvm.x86.tdpbhf8ps.internal
17+
//CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
18+
__tile_dpbhf8ps(&dst, src1, src2);
19+
}
20+
21+
void test_tdphbf8ps(__tile1024i src1, __tile1024i src2, __tile1024i dst) {
22+
//CHECK-LABEL: @test_tdphbf8ps
23+
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
24+
//CHECK-DAG: call x86_amx @llvm.x86.tdphbf8ps.internal
25+
//CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
26+
__tile_dphbf8ps(&dst, src1, src2);
27+
}
28+
29+
void test_tdphf8ps(__tile1024i src1, __tile1024i src2, __tile1024i dst) {
30+
//CHECK-LABEL: @test_tdphf8ps
31+
//CHECK-DAG: call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> {{%.*}})
32+
//CHECK-DAG: call x86_amx @llvm.x86.tdphf8ps.internal
33+
//CHECK-DAG: call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx {{%.*}})
34+
__tile_dphf8ps(&dst, src1, src2);
35+
}
36+

‎llvm/include/llvm/IR/IntrinsicsX86.td

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6168,6 +6168,31 @@ let TargetPrefix = "x86" in {
61686168
Intrinsic<[llvm_x86amx_ty],
61696169
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
61706170
llvm_x86amx_ty, llvm_x86amx_ty], []>;
6171+
6172+
def int_x86_tdpbf8ps_internal :
6173+
ClangBuiltin<"__builtin_ia32_tdpbf8ps_internal">,
6174+
Intrinsic<[llvm_x86amx_ty],
6175+
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
6176+
llvm_x86amx_ty, llvm_x86amx_ty, llvm_x86amx_ty],
6177+
[]>;
6178+
def int_x86_tdpbhf8ps_internal :
6179+
ClangBuiltin<"__builtin_ia32_tdpbhf8ps_internal">,
6180+
Intrinsic<[llvm_x86amx_ty],
6181+
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
6182+
llvm_x86amx_ty, llvm_x86amx_ty, llvm_x86amx_ty],
6183+
[]>;
6184+
def int_x86_tdphbf8ps_internal :
6185+
ClangBuiltin<"__builtin_ia32_tdphbf8ps_internal">,
6186+
Intrinsic<[llvm_x86amx_ty],
6187+
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
6188+
llvm_x86amx_ty, llvm_x86amx_ty, llvm_x86amx_ty],
6189+
[]>;
6190+
def int_x86_tdphf8ps_internal :
6191+
ClangBuiltin<"__builtin_ia32_tdphf8ps_internal">,
6192+
Intrinsic<[llvm_x86amx_ty],
6193+
[llvm_i16_ty, llvm_i16_ty, llvm_i16_ty,
6194+
llvm_x86amx_ty, llvm_x86amx_ty, llvm_x86amx_ty],
6195+
[]>;
61716196
}
61726197

61736198
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86ExpandPseudo.cpp

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,11 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
781781
case X86::PTDPBF16PSV:
782782
case X86::PTDPFP16PSV:
783783
case X86::PTMMULTF32PSV:
784-
case X86::PTTMMULTF32PSV: {
784+
case X86::PTTMMULTF32PSV:
785+
case X86::PTDPBF8PSV:
786+
case X86::PTDPBHF8PSV:
787+
case X86::PTDPHBF8PSV:
788+
case X86::PTDPHF8PSV: {
785789
MI.untieRegOperand(4);
786790
for (unsigned i = 3; i > 0; --i)
787791
MI.removeOperand(i);
@@ -801,6 +805,18 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
801805
case X86::PTTMMULTF32PSV:
802806
Opc = X86::TTMMULTF32PS;
803807
break;
808+
case X86::PTDPBF8PSV:
809+
Opc = X86::TDPBF8PS;
810+
break;
811+
case X86::PTDPBHF8PSV:
812+
Opc = X86::TDPBHF8PS;
813+
break;
814+
case X86::PTDPHBF8PSV:
815+
Opc = X86::TDPHBF8PS;
816+
break;
817+
case X86::PTDPHF8PSV:
818+
Opc = X86::TDPHF8PS;
819+
break;
804820

805821
default:
806822
llvm_unreachable("Unexpected Opcode");

‎llvm/lib/Target/X86/X86InstrAMX.td

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -304,6 +304,37 @@ let Predicates = [HasAMXFP8, In64BitMode] in {
304304
[(int_x86_tdphf8ps timm:$src1, timm:$src2,
305305
timm:$src3)]>;
306306
}
307+
308+
let Constraints = "$src4 = $dst" in {
309+
def PTDPBF8PSV : PseudoI<(outs TILE:$dst),
310+
(ins GR16:$src1, GR16:$src2, GR16:$src3,
311+
TILE:$src4, TILE:$src5, TILE:$src6),
312+
[(set TILE:$dst,
313+
(int_x86_tdpbf8ps_internal GR16:$src1,
314+
GR16:$src2, GR16:$src3, TILE:$src4,
315+
TILE:$src5, TILE:$src6))]>;
316+
def PTDPBHF8PSV : PseudoI<(outs TILE:$dst),
317+
(ins GR16:$src1, GR16:$src2, GR16:$src3,
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TILE:$src4, TILE:$src5, TILE:$src6),
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[(set TILE:$dst,
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(int_x86_tdpbhf8ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
323+
def PTDPHBF8PSV : PseudoI<(outs TILE:$dst),
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(ins GR16:$src1, GR16:$src2, GR16:$src3,
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TILE:$src4, TILE:$src5, TILE:$src6),
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[(set TILE:$dst,
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(int_x86_tdphbf8ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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def PTDPHF8PSV : PseudoI<(outs TILE:$dst),
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(ins GR16:$src1, GR16:$src2, GR16:$src3,
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TILE:$src4, TILE:$src5, TILE:$src6),
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[(set TILE:$dst,
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(int_x86_tdphf8ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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}
307338
}
308339
}
309340

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