Skip to content

Commit 16c61ca

Browse files
committed
[bazel] Port 7fc792c
1 parent 11ba327 commit 16c61ca

File tree

2 files changed

+14
-0
lines changed

2 files changed

+14
-0
lines changed

utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8380,6 +8380,18 @@ cc_library(
83808380
],
83818381
)
83828382

8383+
cc_library(
8384+
name = "SPIRVToLLVMIRTranslation",
8385+
srcs = glob(["lib/Target/LLVMIR/Dialect/SPIRV/*.cpp"]),
8386+
hdrs = glob(["include/mlir/Target/LLVMIR/Dialect/SPIRV/*.h"]),
8387+
includes = ["include"],
8388+
deps = [
8389+
":IR",
8390+
":SPIRVDialect",
8391+
":ToLLVMIRTranslation",
8392+
],
8393+
)
8394+
83838395
cc_library(
83848396
name = "GPUToLLVMIRTranslation",
83858397
srcs = [
@@ -8516,6 +8528,7 @@ cc_library(
85168528
":OpenMPToLLVMIRTranslation",
85178529
":ROCDLTarget",
85188530
":ROCDLToLLVMIRTranslation",
8531+
":SPIRVToLLVMIRTranslation",
85198532
":X86VectorToLLVMIRTranslation",
85208533
],
85218534
)

utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ expand_template(
4141
"@MLIR_ENABLE_CUDA_RUNNER@": "0",
4242
"@MLIR_ENABLE_ROCM_CONVERSIONS@": "0",
4343
"@MLIR_ENABLE_ROCM_RUNNER@": "0",
44+
"@MLIR_ENABLE_SYCL_RUNNER@": "0",
4445
"@MLIR_ENABLE_SPIRV_CPU_RUNNER@": "0",
4546
"@MLIR_ENABLE_VULKAN_RUNNER@": "0",
4647
"@MLIR_ENABLE_BINDINGS_PYTHON@": "0",

0 commit comments

Comments
 (0)