Use setsSCCifResultIsNonZero

Signed-off-by: John Lu <John.Lu@amd.com>

Author: LU-JOHN

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -10587,23 +10587,11 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
       return false;
 
     bool CanOptimize = false;
-    MachineOperand *SccDef =
-        Def->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr);
 
     // For S_OP that set SCC = DST!=0, do the transformation
     //
     //   s_cmp_lg_* (S_OP ...), 0 => (S_OP ...)
-    if (SccDef && Def->getOpcode() != AMDGPU::S_ADD_I32 &&
-        Def->getOpcode() != AMDGPU::S_ADD_U32 &&
-        Def->getOpcode() != AMDGPU::S_ADDC_U32 &&
-        Def->getOpcode() != AMDGPU::S_SUB_I32 &&
-        Def->getOpcode() != AMDGPU::S_SUB_U32 &&
-        Def->getOpcode() != AMDGPU::S_SUBB_U32 &&
-        Def->getOpcode() != AMDGPU::S_MIN_I32 &&
-        Def->getOpcode() != AMDGPU::S_MIN_U32 &&
-        Def->getOpcode() != AMDGPU::S_MAX_I32 &&
-        Def->getOpcode() != AMDGPU::S_MAX_U32 &&
-        Def->getOpcode() != AMDGPU::S_ADDK_I32)
+    if (setsSCCifResultIsNonZero(*Def))
       CanOptimize = true;
 
     // s_cmp_lg_* is redundant because the SCC input value for S_CSELECT* has
@@ -10631,7 +10619,8 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
         return false;
     }
 
-    if (SccDef)
+    if (MachineOperand *SccDef =
+            Def->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr))
       SccDef->setIsDead(false);
 
     CmpInstr.eraseFromParent();

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -709,6 +709,30 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
     }
   }
 
+  static bool setsSCCifResultIsNonZero(const MachineInstr &MI) {
+    if (!MI.findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr))
+      return false;
+    // Compares have no result
+    if (MI.isCompare())
+      return false;
+    switch (MI.getOpcode()) {
+    default:
+      return true;
+    case AMDGPU::S_ADD_I32:
+    case AMDGPU::S_ADD_U32:
+    case AMDGPU::S_ADDC_U32:
+    case AMDGPU::S_SUB_I32:
+    case AMDGPU::S_SUB_U32:
+    case AMDGPU::S_SUBB_U32:
+    case AMDGPU::S_MIN_I32:
+    case AMDGPU::S_MIN_U32:
+    case AMDGPU::S_MAX_I32:
+    case AMDGPU::S_MAX_U32:
+    case AMDGPU::S_ADDK_I32:
+      return false;
+    }
+  }
+
   static bool isEXP(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
   }