Addressing review comments

Author: AnastasiyaChernikova

llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp

@@ -375,9 +375,13 @@ void ExegesisRISCVTarget::processInstructionReservedRegs(
 
   switch (IT.getOpcode()) {
   case RISCV::C_ADDI16SP:
+  case RISCV::C_ADDI4SPN:
     AssignedValue = MCOperand::createReg(RISCV::X2);
     break;
   case RISCV::C_ADDI_NOP:
+  case RISCV::C_LI_HINT:
+  case RISCV::C_LUI_HINT:
+  case RISCV::C_MV_HINT:
   case RISCV::C_ADD_HINT:
   case RISCV::C_SLLI_HINT:
     AssignedValue = MCOperand::createReg(RISCV::X0);

llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp

@@ -57,12 +57,6 @@ computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
       continue;
     const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
     const MCInstrDesc &OtherInstrDesc = OtherInstr.Description;
-    // Ignore instructions that we cannot run.
-    if (OtherInstrDesc.isPseudo() || OtherInstrDesc.usesCustomInsertionHook() ||
-        OtherInstrDesc.isBranch() || OtherInstrDesc.isIndirectBranch() ||
-        OtherInstrDesc.isCall() || OtherInstrDesc.isReturn()) {
-      continue;
-    }
     if (OtherInstr.hasMemoryOperands())
       continue;
     if (!ET.allowAsBackToBack(OtherInstr))