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1 | 1 | // RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \
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2 |
| -// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \ |
3 |
| -// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ |
| 2 | +// RUN: -fnative-half-type -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ |
4 | 3 | // RUN: -DTARGET=dx -DFNATTRS=noundef -DFFNATTRS="nofpclass(nan inf)"
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| 4 | + |
5 | 5 | // RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple dxil-pc-shadermodel6.3-library %s \
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6 |
| -// RUN: -emit-llvm -disable-llvm-passes -o - | \ |
7 |
| -// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \ |
| 6 | +// RUN: -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \ |
8 | 7 | // RUN: -DTARGET=dx -DFNATTRS=noundef -DFFNATTRS="nofpclass(nan inf)"
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| 8 | + |
9 | 9 | // RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple spirv-unknown-vulkan-compute %s \
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10 |
| -// RUN: -fnative-half-type -emit-llvm -disable-llvm-passes -o - | \ |
11 |
| -// RUN: FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ |
| 10 | +// RUN: -fnative-half-type -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,NATIVE_HALF \ |
12 | 11 | // RUN: -DTARGET=spv -DFNATTRS="spir_func noundef" -DFFNATTRS="nofpclass(nan inf)"
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| 12 | + |
13 | 13 | // RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple spirv-unknown-vulkan-compute %s \
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14 |
| -// RUN: -emit-llvm -disable-llvm-passes -o - | \ |
15 |
| -// RUN: FileCheck %s --check-prefixes=CHECK,NO_HALF \ |
| 14 | +// RUN: -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF \ |
16 | 15 | // RUN: -DTARGET=spv -DFNATTRS="spir_func noundef" -DFFNATTRS="nofpclass(nan inf)"
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17 | 16 |
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18 | 17 | #ifdef __HLSL_ENABLE_16_BIT
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19 | 18 | // NATIVE_HALF: define [[FNATTRS]] <4 x i16> {{.*}}test_clamp_short4_mismatch
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20 |
| -// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].sclamp.v4i16 |
| 19 | +// NATIVE_HALF: [[CONV0:%.*]] = insertelement <4 x i16> poison, i16 %{{.*}}, i64 0 |
| 20 | +// NATIVE_HALF: [[CONV1:%.*]] = shufflevector <4 x i16> [[CONV0]], <4 x i16> poison, <4 x i32> zeroinitializer |
| 21 | +// NATIVE_HALF: [[CLAMP:%.*]] = call {{.*}} <4 x i16> @llvm.[[TARGET]].sclamp.v4i16(<4 x i16> %{{.*}}, <4 x i16> %{{.*}}, <4 x i16> [[CONV1]]) |
| 22 | +// NATIVE_HALF: ret <4 x i16> [[CLAMP]] |
21 | 23 | int16_t4 test_clamp_short4_mismatch(int16_t4 p0, int16_t p1) { return clamp(p0, p0,p1); }
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22 | 24 |
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23 | 25 | // NATIVE_HALF: define [[FNATTRS]] <4 x i16> {{.*}}test_clamp_ushort4_mismatch
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24 |
| -// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].uclamp.v4i16 |
| 26 | +// NATIVE_HALF: [[CONV0:%.*]] = insertelement <4 x i16> poison, i16 %{{.*}}, i64 0 |
| 27 | +// NATIVE_HALF: [[CONV1:%.*]] = shufflevector <4 x i16> [[CONV0]], <4 x i16> poison, <4 x i32> zeroinitializer |
| 28 | +// NATIVE_HALF: [[CLAMP:%.*]] = call {{.*}} <4 x i16> @llvm.[[TARGET]].uclamp.v4i16(<4 x i16> %{{.*}}, <4 x i16> %{{.*}}, <4 x i16> [[CONV1]]) |
| 29 | +// NATIVE_HALF: ret <4 x i16> [[CLAMP]] |
25 | 30 | uint16_t4 test_clamp_ushort4_mismatch(uint16_t4 p0, uint16_t p1) { return clamp(p0, p0,p1); }
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26 | 31 | #endif
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27 | 32 |
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28 | 33 | // CHECK: define [[FNATTRS]] <4 x i32> {{.*}}test_clamp_int4_mismatch
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29 |
| -// CHECK: call <4 x i32> @llvm.[[TARGET]].sclamp.v4i32 |
| 34 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x i32> poison, i32 %{{.*}}, i64 0 |
| 35 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x i32> [[CONV0]], <4 x i32> poison, <4 x i32> zeroinitializer |
| 36 | +// CHECK: [[CLAMP:%.*]] = call {{.*}} <4 x i32> @llvm.[[TARGET]].sclamp.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> [[CONV1]]) |
| 37 | +// CHECK: ret <4 x i32> [[CLAMP]] |
30 | 38 | int4 test_clamp_int4_mismatch(int4 p0, int p1) { return clamp(p0, p0,p1); }
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31 | 39 |
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32 | 40 | // CHECK: define [[FNATTRS]] <4 x i32> {{.*}}test_clamp_uint4_mismatch
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33 |
| -// CHECK: call <4 x i32> @llvm.[[TARGET]].uclamp.v4i32 |
| 41 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x i32> poison, i32 %{{.*}}, i64 0 |
| 42 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x i32> [[CONV0]], <4 x i32> poison, <4 x i32> zeroinitializer |
| 43 | +// CHECK: [[CLAMP:%.*]] = call {{.*}} <4 x i32> @llvm.[[TARGET]].uclamp.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> [[CONV1]]) |
| 44 | +// CHECK: ret <4 x i32> [[CLAMP]] |
34 | 45 | uint4 test_clamp_uint4_mismatch(uint4 p0, uint p1) { return clamp(p0, p0,p1); }
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35 | 46 |
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36 | 47 | // CHECK: define [[FNATTRS]] <4 x i64> {{.*}}test_clamp_long4_mismatch
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37 |
| -// CHECK: call <4 x i64> @llvm.[[TARGET]].sclamp.v4i64 |
| 48 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x i64> poison, i64 %{{.*}}, i64 0 |
| 49 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x i64> [[CONV0]], <4 x i64> poison, <4 x i32> zeroinitializer |
| 50 | +// CHECK: [[CLAMP:%.*]] = call {{.*}} <4 x i64> @llvm.[[TARGET]].sclamp.v4i64(<4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> [[CONV1]]) |
| 51 | +// CHECK: ret <4 x i64> [[CLAMP]] |
38 | 52 | int64_t4 test_clamp_long4_mismatch(int64_t4 p0, int64_t p1) { return clamp(p0, p0,p1); }
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39 | 53 |
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40 | 54 | // CHECK: define [[FNATTRS]] <4 x i64> {{.*}}test_clamp_ulong4_mismatch
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41 |
| -// CHECK: call <4 x i64> @llvm.[[TARGET]].uclamp.v4i64 |
| 55 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x i64> poison, i64 %{{.*}}, i64 0 |
| 56 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x i64> [[CONV0]], <4 x i64> poison, <4 x i32> zeroinitializer |
| 57 | +// CHECK: [[CLAMP:%.*]] = call {{.*}} <4 x i64> @llvm.[[TARGET]].uclamp.v4i64(<4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i64> [[CONV1]]) |
| 58 | +// CHECK: ret <4 x i64> [[CLAMP]] |
42 | 59 | uint64_t4 test_clamp_ulong4_mismatch(uint64_t4 p0, uint64_t p1) { return clamp(p0, p0,p1); }
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43 | 60 |
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44 | 61 | // NATIVE_HALF: define [[FNATTRS]] [[FFNATTRS]] <4 x half> {{.*}}test_clamp_half4_mismatch
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45 |
| -// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.[[TARGET]].nclamp.v4f16 |
| 62 | +// NATIVE_HALF: [[CONV0:%.*]] = insertelement <4 x half> poison, half %{{.*}}, i64 0 |
| 63 | +// NATIVE_HALF: [[CONV1:%.*]] = shufflevector <4 x half> [[CONV0]], <4 x half> poison, <4 x i32> zeroinitializer |
| 64 | +// NATIVE_HALF: [[CLAMP:%.*]] = call reassoc nnan ninf nsz arcp afn {{.*}} <4 x half> @llvm.[[TARGET]].nclamp.v4f16(<4 x half> %{{.*}}, <4 x half> %{{.*}}, <4 x half> [[CONV1]]) |
| 65 | +// NATIVE_HALF: ret <4 x half> [[CLAMP]] |
46 | 66 | // NO_HALF: define [[FNATTRS]] [[FFNATTRS]] <4 x float> {{.*}}test_clamp_half4_mismatch
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47 |
| -// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32( |
| 67 | +// NO_HALF: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 |
| 68 | +// NO_HALF: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer |
| 69 | +// NO_HALF: [[CLAMP:%.*]] = call reassoc nnan ninf nsz arcp afn {{.*}} <4 x float> @llvm.[[TARGET]].nclamp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[CONV1]]) |
| 70 | +// NO_HALF: ret <4 x float> [[CLAMP]] |
48 | 71 | half4 test_clamp_half4_mismatch(half4 p0, half p1) { return clamp(p0, p0,p1); }
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49 | 72 |
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50 | 73 | // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x float> {{.*}}test_clamp_float4_mismatch
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51 |
| -// CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32 |
| 74 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 |
| 75 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer |
| 76 | +// CHECK: [[CLAMP:%.*]] = call reassoc nnan ninf nsz arcp afn {{.*}} <4 x float> @llvm.[[TARGET]].nclamp.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[CONV1]]) |
| 77 | +// CHECK: ret <4 x float> [[CLAMP]] |
52 | 78 | float4 test_clamp_float4_mismatch(float4 p0, float p1) { return clamp(p0, p0,p1); }
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53 | 79 |
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54 |
| -// CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_clamp_double4_mismatch |
55 |
| -// CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64 |
56 |
| -double4 test_clamp_double4_mismatch(double4 p0, double p1) { return clamp(p0, p0,p1); } |
| 80 | + |
| 81 | +// CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_clamp_double4_mismatch1 |
| 82 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 |
| 83 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer |
| 84 | +// CHECK: [[CLAMP:%.*]] = call reassoc nnan ninf nsz arcp afn {{.*}} <4 x double> @llvm.[[TARGET]].nclamp.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[CONV1]]) |
| 85 | +// CHECK: ret <4 x double> [[CLAMP]] |
| 86 | +double4 test_clamp_double4_mismatch1(double4 p0, double p1) { return clamp(p0, p0,p1); } |
57 | 87 | // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_clamp_double4_mismatch2
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58 |
| -// CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64 |
| 88 | +// CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 |
| 89 | +// CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer |
| 90 | +// CHECK: [[CLAMP:%.*]] = call reassoc nnan ninf nsz arcp afn {{.*}} <4 x double> @llvm.[[TARGET]].nclamp.v4f64(<4 x double> %{{.*}}, <4 x double> [[CONV1]], <4 x double> %{{.*}}) |
| 91 | +// CHECK: ret <4 x double> [[CLAMP]] |
59 | 92 | double4 test_clamp_double4_mismatch2(double4 p0, double p1) { return clamp(p0, p1,p0); }
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60 | 93 |
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61 | 94 | // CHECK: define [[FNATTRS]] <3 x i32> {{.*}}test_overloads3
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62 |
| -// CHECK: call <3 x i32> @llvm.[[TARGET]].uclamp.v3i32 |
| 95 | +// CHECK: [[CONV0:%.*]] = insertelement <3 x i32> poison, i32 %{{.*}}, i64 0 |
| 96 | +// CHECK: [[CONV1:%.*]] = shufflevector <3 x i32> [[CONV0]], <3 x i32> poison, <3 x i32> zeroinitializer |
| 97 | +// CHECK: [[CONV2:%.*]] = insertelement <3 x i32> poison, i32 %{{.*}}, i64 0 |
| 98 | +// CHECK: [[CONV3:%.*]] = shufflevector <3 x i32> [[CONV2]], <3 x i32> poison, <3 x i32> zeroinitializer |
| 99 | +// CHECK: [[CLAMP:%.*]] = call {{.*}} <3 x i32> @llvm.[[TARGET]].uclamp.v3i32(<3 x i32> %{{.*}}, <3 x i32> [[CONV1]], <3 x i32> [[CONV3]]) |
| 100 | +// CHECK: ret <3 x i32> [[CLAMP]] |
63 | 101 | uint3 test_overloads3(uint3 p0, uint p1, uint p2) { return clamp(p0, p1, p2); }
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