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7 | 7 | ; Combine tests involving SSE41 target shuffles (BLEND,INSERTPS,MOVZX) |
8 | 8 |
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9 | 9 | declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) |
| 10 | +declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) |
10 | 11 |
|
11 | 12 | define <16 x i8> @combine_vpshufb_as_movzx(<16 x i8> %a0) { |
12 | 13 | ; SSE-LABEL: combine_vpshufb_as_movzx: |
@@ -58,6 +59,25 @@ define <4 x i32> @combine_blend_of_permutes_v4i32(<2 x i64> %a0, <2 x i64> %a1) |
58 | 59 | ret <4 x i32> %r |
59 | 60 | } |
60 | 61 |
|
| 62 | +define <4 x float> @freeze_insertps(<4 x float> %a0, <4 x float> %a1) { |
| 63 | +; SSE-LABEL: freeze_insertps: |
| 64 | +; SSE: # %bb.0: |
| 65 | +; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] |
| 66 | +; SSE-NEXT: insertps {{.*#+}} xmm1 = xmm0[1],xmm1[1,2,3] |
| 67 | +; SSE-NEXT: movaps %xmm1, %xmm0 |
| 68 | +; SSE-NEXT: retq |
| 69 | +; |
| 70 | +; AVX-LABEL: freeze_insertps: |
| 71 | +; AVX: # %bb.0: |
| 72 | +; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] |
| 73 | +; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[1],xmm1[1,2,3] |
| 74 | +; AVX-NEXT: retq |
| 75 | + %s0 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 16) |
| 76 | + %f0 = freeze <4 x float> %s0 |
| 77 | + %s1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a1, <4 x float> %f0, i8 64) |
| 78 | + ret <4 x float> %s1 |
| 79 | +} |
| 80 | + |
61 | 81 | define <16 x i8> @PR50049(ptr %p1, ptr %p2) { |
62 | 82 | ; SSE-LABEL: PR50049: |
63 | 83 | ; SSE: # %bb.0: |
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