Skip to content

Commit 07bcd95

Browse files
aadeshps-mcwaadeshps-mcw
committed
--Added support for the extension SPV_INTEL_fpga_buffer_location
1 parent 6cb087a commit 07bcd95

File tree

9 files changed

+234
-2
lines changed

9 files changed

+234
-2
lines changed

‎llvm/docs/SPIRVUsage.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
217217
- Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix.
218218
* - ``SPV_INTEL_int4``
219219
- Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
220+
* - ``SPV_INTEL_fpga_buffer_location``
221+
- Adds a pointer decoration for FPGA targets, indicating that a global memory pointer accesses only a specific physical memory location.
220222

221223
To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
222224

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,15 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
363363
buildOpDecorate(VRegs[i][0], MIRBuilder, Decoration, {});
364364
}
365365

366+
if (MDNode *Node = F.getMetadata("kernel_arg_buffer_location")) {
367+
int64_t BufferLoc =
368+
processKernelArgBufferLocation(F, Node, i, VRegs, -1);
369+
if (BufferLoc != -1)
370+
buildOpDecorate(VRegs[i][0], MIRBuilder,
371+
SPIRV::Decoration::BufferLocationINTEL,
372+
{static_cast<uint32_t>(BufferLoc)});
373+
}
374+
366375
MDNode *Node = F.getMetadata("spirv.ParameterDecorations");
367376
if (Node && i < Node->getNumOperands() &&
368377
isa<MDNode>(Node->getOperand(i))) {

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
100100
SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
101101
{"SPV_INTEL_2d_block_io",
102102
SPIRV::Extension::Extension::SPV_INTEL_2d_block_io},
103-
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4}};
103+
{"SPV_INTEL_int4", SPIRV::Extension::Extension::SPV_INTEL_int4},
104+
{"SPV_INTEL_fpga_buffer_location",
105+
SPIRV::Extension::Extension::SPV_INTEL_fpga_buffer_location}};
104106

105107
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
106108
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVMetadata.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
//===----------------------------------------------------------------------===//
1313

1414
#include "SPIRVMetadata.h"
15+
#include "llvm/IR/Constants.h"
1516

1617
using namespace llvm;
1718

@@ -82,4 +83,15 @@ MDString *getOCLKernelArgTypeQual(const Function &F, unsigned ArgIdx) {
8283
return getOCLKernelArgAttribute(F, ArgIdx, "kernel_arg_type_qual");
8384
}
8485

86+
int64_t processKernelArgBufferLocation(
87+
const Function &F, MDNode *Node, int i,
88+
llvm::ArrayRef<llvm::ArrayRef<llvm::Register>> VRegs, int64_t BufferLoc) {
89+
if (Node && static_cast<unsigned>(i) < Node->getNumOperands())
90+
if (auto *CI = dyn_cast<ConstantInt>(
91+
cast<ConstantAsMetadata>(Node->getOperand(i))->getValue()))
92+
if (F.getFunctionType()->getParamType(i)->isPointerTy())
93+
return CI->getSExtValue();
94+
return BufferLoc;
95+
}
96+
8597
} // namespace llvm

‎llvm/lib/Target/SPIRV/SPIRVMetadata.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVMETADATA_H
1515
#define LLVM_LIB_TARGET_SPIRV_SPIRVMETADATA_H
1616

17+
#include "llvm/CodeGen/Register.h"
1718
#include "llvm/IR/Metadata.h"
1819
#include "llvm/IR/Module.h"
1920

@@ -25,6 +26,8 @@ namespace llvm {
2526

2627
MDString *getOCLKernelArgAccessQual(const Function &F, unsigned ArgIdx);
2728
MDString *getOCLKernelArgTypeQual(const Function &F, unsigned ArgIdx);
28-
29+
int64_t processKernelArgBufferLocation(
30+
const Function &F, MDNode *Node, int i,
31+
llvm::ArrayRef<llvm::ArrayRef<llvm::Register>> VRegs, int64_t BufferLoc);
2932
} // namespace llvm
3033
#endif // LLVM_LIB_TARGET_SPIRV_METADATA_H

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -920,6 +920,9 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex,
920920
} else if (Dec == SPIRV::Decoration::FPMaxErrorDecorationINTEL) {
921921
Reqs.addRequirements(SPIRV::Capability::FPMaxErrorINTEL);
922922
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fp_max_error);
923+
} else if (Dec == SPIRV::Decoration::BufferLocationINTEL) {
924+
Reqs.addRequirements(SPIRV::Capability::FPGABufferLocationINTEL);
925+
Reqs.addExtension(SPIRV::Extension::SPV_INTEL_fpga_buffer_location);
923926
}
924927
}
925928

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,7 @@ defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
318318
defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
319319
defm SPV_INTEL_2d_block_io : ExtensionOperand<122>;
320320
defm SPV_INTEL_int4 : ExtensionOperand<123>;
321+
defm SPV_INTEL_fpga_buffer_location : ExtensionOperand<124>;
321322

322323
//===----------------------------------------------------------------------===//
323324
// Multiclass used to define Capabilities enum values and at the same time
@@ -525,6 +526,7 @@ defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d
525526
defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
526527
defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>;
527528
defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>;
529+
defm FPGABufferLocationINTEL : CapabilityOperand<5920, 0, 0, [SPV_INTEL_fpga_buffer_location], []>;
528530

529531
//===----------------------------------------------------------------------===//
530532
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1276,6 +1278,7 @@ defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [Functio
12761278
defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
12771279
defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
12781280
defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
1281+
defm BufferLocationINTEL : DecorationOperand<5921, 0, 0, [SPV_INTEL_fpga_buffer_location], [FPGABufferLocationINTEL]>;
12791282

12801283
//===----------------------------------------------------------------------===//
12811284
// Multiclass used to define BuiltIn enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_buffer_location/FPGABufferLocation.ll

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_buffer_location %s -o %t.spt
2+
; RUN: FileCheck %s --input-file=%t.spt
3+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_buffer_location %s -o - -filetype=obj | spirv-val %}
4+
5+
; CHECK-DAG: OpCapability FPGABufferLocationINTEL
6+
; CHECK-DAG: OpExtension "SPV_INTEL_fpga_buffer_location"
7+
; CHECK-DAG: OpName %[[#ARGA:]] "a"
8+
; CHECK-DAG: OpName %[[#ARGB:]] "b"
9+
; CHECK-DAG: OpName %[[#ARGC:]] "c"
10+
; CHECK-DAG: OpName %[[#ARGD:]] "d"
11+
; CHECK-DAG: OpName %[[#ARGE:]] "e"
12+
; CHECK-NOT: OpDecorate %[[#ARGC]] BufferLocationINTEL -1
13+
; CHECK-NOT: OpDecorate %[[#ARGC]] BufferLocationINTEL -1
14+
; CHECK-DAG: OpDecorate %[[#ARGA]] BufferLocationINTEL 1
15+
; CHECK-DAG: OpDecorate %[[#ARGB]] BufferLocationINTEL 2
16+
; CHECK-NOT: OpDecorate %[[#ARGD]] BufferLocationINTEL -1
17+
; CHECK-NOT: OpDecorate %[[#ARGE]] BufferLocationINTEL 3
18+
; CHECK-DAG: OpDecorate %[[#]] BufferLocationINTEL 123456789
19+
20+
; CHECK-DAG: %[[#]] = OpFunction
21+
; CHECK-DAG: %[[#ARGA]] = OpFunctionParameter %[[#]]
22+
; CHECK-DAG: %[[#ARGB]] = OpFunctionParameter %[[#]]
23+
; CHECK-DAG: %[[#ARGC]] = OpFunctionParameter %[[#]]
24+
25+
26+
27+
28+
%struct.MyIP = type { ptr addrspace(4) }
29+
30+
@.str.4 = internal unnamed_addr addrspace(1) constant [19 x i8] c"{5921:\22123456789\22}\00"
31+
@.str.1 = internal unnamed_addr addrspace(1) constant [9 x i8] c"main.cpp\00"
32+
33+
; Function Attrs: nounwind
34+
define spir_kernel void @test(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, i32 %d, i32 %e) local_unnamed_addr !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_buffer_location !6
35+
{
36+
entry:
37+
ret void
38+
}
39+
40+
; test1 : direct on kernel argument
41+
; Function Attrs: norecurse nounwind readnone
42+
define spir_kernel void @test.1(ptr addrspace(4) %a) #0
43+
{
44+
entry:
45+
%0 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %a, ptr addrspace(1) getelementptr inbounds ([19 x i8], ptr addrspace(1) @.str.4, i32 0, i32 0), ptr addrspace(1) getelementptr inbounds ([9 x i8], ptr addrspace(1) @.str.1, i32 0, i32 0), i32 7, ptr addrspace(1) null)
46+
store i8 0, ptr addrspace(4) %0, align 8
47+
ret void
48+
}
49+
50+
$test.2 = comdat any
51+
; test2 : general
52+
; Function Attrs: convergent mustprogress norecurse
53+
define weak_odr dso_local spir_kernel void @test.2(ptr addrspace(1) align 4 %arg_a) #0 comdat !kernel_arg_buffer_location !7 {
54+
entry:
55+
%this.addr.i = alloca ptr addrspace(4), align 8
56+
%arg_a.addr = alloca ptr addrspace(1), align 8
57+
%MyIP = alloca %struct.MyIP, align 8
58+
%arg_a.addr.ascast = addrspacecast ptr %arg_a.addr to ptr addrspace(4)
59+
%MyIP.ascast = addrspacecast ptr %MyIP to ptr addrspace(4)
60+
store ptr addrspace(1) %arg_a, ptr addrspace(4) %arg_a.addr.ascast, align 8
61+
%a = getelementptr inbounds %struct.MyIP, ptr addrspace(4) %MyIP.ascast, i32 0, i32 0
62+
%0 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %a, ptr addrspace(1) getelementptr inbounds ([33 x i8], ptr addrspace(1) @.str.4, i32 0, i32 0), ptr addrspace(1) getelementptr inbounds ([9 x i8], ptr addrspace(1) @.str.1, i32 0, i32 0), i32 7, ptr addrspace(1) null)
63+
%b = load ptr addrspace(1), ptr addrspace(4) %arg_a.addr.ascast, align 8
64+
%1 = addrspacecast ptr addrspace(1) %b to ptr addrspace(4)
65+
store ptr addrspace(4) %1, ptr addrspace(4) %0, align 8
66+
%this.addr.ascast.i = addrspacecast ptr %this.addr.i to ptr addrspace(4)
67+
store ptr addrspace(4) %MyIP.ascast, ptr addrspace(4) %this.addr.ascast.i, align 8
68+
%this1.i = load ptr addrspace(4), ptr addrspace(4) %this.addr.ascast.i, align 8
69+
%a.i = getelementptr inbounds %struct.MyIP, ptr addrspace(4) %this1.i, i32 0, i32 0
70+
%2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %a.i, ptr addrspace(1) getelementptr inbounds ([19 x i8], ptr addrspace(1) @.str.4, i32 0, i32 0), ptr addrspace(1) getelementptr inbounds ([9 x i8], ptr addrspace(1) @.str.1, i32 0, i32 0), i32 7, ptr addrspace(1) null)
71+
%3 = load ptr addrspace(4), ptr addrspace(4) %2, align 8
72+
%4 = load i32, ptr addrspace(4) %3, align 4
73+
%inc.i = add nsw i32 %4, 1
74+
store i32 %inc.i, ptr addrspace(4) %3, align 4
75+
ret void
76+
}
77+
78+
; test3 : memcpy
79+
; Function Attrs: convergent mustprogress norecurse
80+
define spir_kernel void @test.3(ptr addrspace(1) align 4 %arg_a, ptr %arg_b) {
81+
entry:
82+
%this.addr.i = alloca ptr addrspace(4), align 8
83+
%arg_a.addr = alloca ptr addrspace(1), align 8
84+
%MyIP = alloca %struct.MyIP, align 8
85+
%arg_a.addr.ascast = addrspacecast ptr %arg_a.addr to ptr addrspace(4)
86+
%MyIP.ascast = addrspacecast ptr %MyIP to ptr addrspace(4)
87+
store ptr addrspace(1) %arg_a, ptr addrspace(4) %arg_a.addr.ascast, align 8
88+
%a = getelementptr inbounds %struct.MyIP, ptr addrspace(4) %MyIP.ascast, i32 0, i32 0
89+
%0 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %a, ptr addrspace(1) getelementptr inbounds ([19 x i8], ptr addrspace(1) @.str.4, i32 0, i32 0), ptr addrspace(1) getelementptr inbounds ([9 x i8], ptr addrspace(1) @.str.1, i32 0, i32 0), i32 7, ptr addrspace(1) null)
90+
call void @llvm.memcpy.p4.p0(ptr addrspace(4) %0, ptr %arg_b, i64 4, i1 false)
91+
ret void
92+
}
93+
94+
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
95+
declare ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4), ptr addrspace(1), ptr addrspace(1), i32, ptr addrspace(1)) #1
96+
97+
; Function Attrs: argmemonly nofree nounwind willreturn
98+
declare void @llvm.memcpy.p4.p0(ptr addrspace(4) noalias captures(none) writeonly, ptr noalias captures(none) readonly, i64, i1 immarg) #2
99+
100+
!opencl.enable.FP_CONTRACT = !{}
101+
!opencl.ocl.version = !{!0}
102+
!opencl.spir.version = !{!0}
103+
!opencl.used.extensions = !{!1}
104+
!opencl.used.optional.core.features = !{!1}
105+
!opencl.compiler.options = !{!1}
106+
!llvm.ident = !{!2}
107+
108+
!0 = !{i32 2, i32 0}
109+
!1 = !{}
110+
!2 = !{!""}
111+
!3 = !{i32 1, i32 1, i32 1}
112+
!4 = !{!"none", !"none", !"none"}
113+
!5 = !{!"int*", !"float*", !"int*"}
114+
!6 = !{i32 1, i32 2, i32 -1, i32 -1, i32 3}
115+
!7 = !{i32 -1}

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fpga_buffer_location/sycl-buffer-location-with-ptr-annotation.ll

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_buffer_location %s -o %t.spt
2+
; RUN: FileCheck %s --input-file=%t.spt
3+
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_buffer_location %s -o - -filetype=obj | spirv-val %}
4+
5+
; CHECK-DAG: OpDecorate %[[#Ptr1:]] BufferLocationINTEL 0
6+
; CHECK-DAG: OpDecorate %[[#Ptr2:]] BufferLocationINTEL 0
7+
8+
; CHECK-DAG: %[[#Ptr1]] = OpLoad %[[#]]
9+
; CHECK-DAG: OpReturnValue %[[#Ptr1]]
10+
11+
; CHECK-DAG: %[[#Bitcast:]] = OpBitcast %[[#]] %[[#]]
12+
; CHECK-DAG: %[[#Ptr2]] = OpInBoundsPtrAccessChain %[[#]] %[[#Bitcast]] %[[#]] %[[#]]
13+
; CHECK-DAG: OpReturnValue %[[#Ptr2]]
14+
15+
16+
%struct.MyIP = type <{ ptr addrspace(4), i32, [4 x i8] }>
17+
18+
$_ZNK4MyIPclEv = comdat any
19+
20+
$_Z8annotateIiEPT_S1_ = comdat any
21+
22+
$_Z9annotate2IiEPT_S1_ = comdat any
23+
24+
@.str = private unnamed_addr addrspace(1) constant [16 x i8] c"sycl-properties\00", section "llvm.metadata"
25+
@.str.1 = private unnamed_addr addrspace(1) constant [9 x i8] c"test.cpp\00", section "llvm.metadata"
26+
@.str.2 = private unnamed_addr addrspace(1) constant [21 x i8] c"sycl-buffer-location\00", section "llvm.metadata"
27+
@.str.3 = private unnamed_addr addrspace(1) constant [2 x i8] c"0\00", section "llvm.metadata"
28+
@.args = private unnamed_addr addrspace(1) constant { ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @.str.2, ptr addrspace(1) @.str.3 }, section "llvm.metadata"
29+
@.str.4 = private unnamed_addr addrspace(1) constant [11 x i8] c"{5921:\220\22}\00", section "llvm.metadata"
30+
31+
; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
32+
define linkonce_odr dso_local spir_func void @_ZNK4MyIPclEv(ptr addrspace(4) %this) comdat align 2 !srcloc !8 {
33+
entry:
34+
%call1 = call spir_func noundef ptr addrspace(4) @_Z8annotateIiEPT_S1_(ptr addrspace(4) noundef %this)
35+
%call2 = call spir_func noundef ptr addrspace(4) @_Z9annotate2IiEPT_S1_(ptr addrspace(4) noundef %this)
36+
ret void
37+
}
38+
39+
; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
40+
define linkonce_odr dso_local spir_func noundef ptr addrspace(4) @_Z8annotateIiEPT_S1_(ptr addrspace(4) noundef %ptr) comdat !srcloc !9 {
41+
entry:
42+
%retval = alloca ptr addrspace(4), align 8
43+
%ptr.addr = alloca ptr addrspace(4), align 8
44+
%retval.ascast = addrspacecast ptr %retval to ptr addrspace(4)
45+
%ptr.addr.ascast = addrspacecast ptr %ptr.addr to ptr addrspace(4)
46+
store ptr addrspace(4) %ptr, ptr addrspace(4) %ptr.addr.ascast, align 8
47+
%0 = load ptr addrspace(4), ptr addrspace(4) %ptr.addr.ascast, align 8
48+
%1 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %0, ptr addrspace(1) @.str.4, ptr addrspace(1) @.str.1, i32 25, ptr addrspace(1) null)
49+
ret ptr addrspace(4) %1
50+
}
51+
52+
; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone
53+
define linkonce_odr dso_local spir_func noundef ptr addrspace(4) @_Z9annotate2IiEPT_S1_(ptr addrspace(4) noundef %ptr) comdat !srcloc !9 {
54+
entry:
55+
%retval = alloca ptr addrspace(4), align 8
56+
%ptr.addr = alloca ptr addrspace(4), align 8
57+
%retval.ascast = addrspacecast ptr %retval to ptr addrspace(4)
58+
%ptr.addr.ascast = addrspacecast ptr %ptr.addr to ptr addrspace(4)
59+
store ptr addrspace(4) %ptr, ptr addrspace(4) %ptr.addr.ascast, align 8
60+
%0 = load ptr addrspace(4), ptr addrspace(4) %ptr.addr.ascast, align 8
61+
%1 = getelementptr inbounds %struct.MyIP, ptr addrspace(4) %0, i32 0, i32 0
62+
%2 = call ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4) %1, ptr addrspace(1) @.str.4, ptr addrspace(1) @.str.1, i32 25, ptr addrspace(1) null)
63+
ret ptr addrspace(4) %2
64+
}
65+
66+
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
67+
declare ptr addrspace(4) @llvm.ptr.annotation.p4.p1(ptr addrspace(4), ptr addrspace(1), ptr addrspace(1), i32, ptr addrspace(1))
68+
69+
!llvm.module.flags = !{!0, !1}
70+
!opencl.spir.version = !{!2}
71+
!spirv.Source = !{!3}
72+
!llvm.ident = !{!4}
73+
74+
!0 = !{i32 1, !"wchar_size", i32 4}
75+
!1 = !{i32 7, !"frame-pointer", i32 2}
76+
!2 = !{i32 1, i32 2}
77+
!3 = !{i32 4, i32 100000}
78+
!4 = !{!"Intel(R) oneAPI DPC++/C++ Compiler 2024.2.0 (2024.x.0.YYYYMMDD)"}
79+
!5 = !{i32 717}
80+
!6 = !{i32 -1, i32 -1}
81+
!7 = !{}
82+
!8 = !{i32 1004}
83+
!9 = !{i32 563}

0 commit comments

Comments
 (0)