[CIR][CIRGen] Move CIRGen types into clang::CIRGen (#1082)

#1025 explains why we want to move
the CIR dialect from the `mlir::cir` to the `cir` namespace. To avoid
overloading the `cir` namespace too much afterwards, move all symbols
whose equivalents live inside the `clang::CodeGen` namespace to a new
`clang::CIRGen` namespace, so that we match the original CodeGen's
structure more closely.

There's some symbols that live under `clang/include/clang/CIR` whose
equivalents live in `clang/lib/CodeGen` and are in the `clang::CodeGen`
namespace. We have these symbols in a common location since they're also
used by lowering, so I've also left them in the `cir` namespace. Those
symbols are:
- AArch64ABIKind
- ABIArgInfo
- FnInfoOpts
- TypeEvaluationKind
- X86AVXABILevel

This is a pretty large PR out of necessity. To make it slightly more
reviewable, I've split it out into three commits (which will be squashed
together when the PR lands):
- The first commit manually switches places to the `clang::CIRGen`
  namespace. This has to be manual because we only want to move things
  selectively.
- The second commit adjusts namespace prefixes to make builds work. I
  ran https://gist.github.com/smeenai/f4dd441fb61c53e835c4e6057f8c322f
  to make this change. The script is idempotent, and I added
  substitutions one at a time and reviewed each one afterwards (using
  `git diff --color-words=.`) to ensure only intended changes were being
  made.
- The third commit runs `git clang-format`.

Because I went one-by-one with all my substitutions and checked each one
afterwards, I'm pretty confident in the validity of all the changes
(despite the size of the PR).

Author: smeenai

clang/include/clang/CIR/CIRGenerator.h

@@ -34,12 +34,14 @@ namespace clang {
 class ASTContext;
 class DeclGroupRef;
 class FunctionDecl;
-} // namespace clang
 
-namespace cir {
+namespace CIRGen {
 class CIRGenModule;
 class CIRGenTypes;
+} // namespace CIRGen
+} // namespace clang
 
+namespace cir {
 class CIRGenerator : public clang::ASTConsumer {
   virtual void anchor();
   clang::DiagnosticsEngine &Diags;
@@ -70,7 +72,7 @@ class CIRGenerator : public clang::ASTConsumer {
 
 protected:
   std::unique_ptr<mlir::MLIRContext> mlirCtx;
-  std::unique_ptr<CIRGenModule> CGM;
+  std::unique_ptr<clang::CIRGen::CIRGenModule> CGM;
 
 private:
   llvm::SmallVector<clang::FunctionDecl *, 8> DeferredInlineMemberFuncDefs;

clang/lib/CIR/CodeGen/ABIInfo.h

@@ -11,9 +11,8 @@
 
 #include "clang/AST/Type.h"
 
-namespace cir {
+namespace clang::CIRGen {
 
-class ABIArgInfo;
 class CIRGenCXXABI;
 class CIRGenFunctionInfo;
 class CIRGenTypes;
@@ -42,6 +41,6 @@ class ABIInfo {
   bool isPromotableIntegerTypeForABI(clang::QualType Ty) const;
 };
 
-} // namespace cir
+} // namespace clang::CIRGen
 
 #endif

clang/lib/CIR/CodeGen/Address.h

@@ -21,7 +21,7 @@
 
 #include "mlir/IR/Value.h"
 
-namespace cir {
+namespace clang::CIRGen {
 
 // Indicates whether a pointer is known not to be null.
 enum KnownNonNull_t { NotKnownNonNull, KnownNonNull };
@@ -143,6 +143,6 @@ class Address {
   }
 };
 
-} // namespace cir
+} // namespace clang::CIRGen
 
 #endif // LLVM_CLANG_LIB_CIR_ADDRESS_H

clang/lib/CIR/CodeGen/CIRAsm.cpp

@@ -5,8 +5,8 @@
 #include "TargetInfo.h"
 #include "clang/CIR/MissingFeatures.h"
 
-using namespace cir;
 using namespace clang;
+using namespace clang::CIRGen;
 using namespace mlir::cir;
 
 static bool isAggregateType(mlir::Type typ) {
@@ -285,7 +285,7 @@ static void buildAsmStores(CIRGenFunction &CGF, const AsmStmt &S,
     mlir::Type TruncTy = ResultTruncRegTypes[i];
 
     if ((i < ResultRegIsFlagReg.size()) && ResultRegIsFlagReg[i]) {
-      assert(!MissingFeatures::asmLLVMAssume());
+      assert(!cir::MissingFeatures::asmLLVMAssume());
     }
 
     // If the result type of the LLVM IR asm doesn't match the result type of
@@ -311,7 +311,7 @@ static void buildAsmStores(CIRGenFunction &CGF, const AsmStmt &S,
       } else if (isa<mlir::cir::IntType>(TruncTy)) {
         Tmp = Builder.createIntCast(Tmp, TruncTy);
       } else if (false /*TruncTy->isVectorTy()*/) {
-        assert(!MissingFeatures::asmVectorType());
+        assert(!cir::MissingFeatures::asmVectorType());
       }
     }
 
@@ -468,7 +468,7 @@ mlir::LogicalResult CIRGenFunction::buildAsmStmt(const AsmStmt &S) {
       }
 
       // Update largest vector width for any vector types.
-      assert(!MissingFeatures::asmVectorType());
+      assert(!cir::MissingFeatures::asmVectorType());
     } else {
       Address DestAddr = Dest.getAddress();
 
@@ -504,7 +504,7 @@ mlir::LogicalResult CIRGenFunction::buildAsmStmt(const AsmStmt &S) {
         Arg = builder.createBitcast(Arg, AdjTy);
 
       // Update largest vector width for any vector types.
-      assert(!MissingFeatures::asmVectorType());
+      assert(!cir::MissingFeatures::asmVectorType());
 
       // Only tie earlyclobber physregs.
       if (Info.allowsRegister() && (GCCReg.empty() || Info.earlyClobber()))
@@ -521,7 +521,7 @@ mlir::LogicalResult CIRGenFunction::buildAsmStmt(const AsmStmt &S) {
   // If this is a Microsoft-style asm blob, store the return registers (EAX:EDX)
   // to the return value slot. Only do this when returning in registers.
   if (isa<MSAsmStmt>(&S)) {
-    const ABIArgInfo &RetAI = CurFnInfo->getReturnInfo();
+    const cir::ABIArgInfo &RetAI = CurFnInfo->getReturnInfo();
     if (RetAI.isDirect() || RetAI.isExtend()) {
       // Make a fake lvalue for the return value slot.
       LValue ReturnSlot = makeAddrLValue(ReturnValue, FnRetTy);
@@ -593,7 +593,7 @@ mlir::LogicalResult CIRGenFunction::buildAsmStmt(const AsmStmt &S) {
           << InputExpr->getType() << InputConstraint;
 
     // Update largest vector width for any vector types.
-    assert(!MissingFeatures::asmVectorType());
+    assert(!cir::MissingFeatures::asmVectorType());
 
     ArgTypes.push_back(Arg.getType());
     ArgElemTypes.push_back(ArgElemType);
@@ -636,11 +636,11 @@ mlir::LogicalResult CIRGenFunction::buildAsmStmt(const AsmStmt &S) {
       HasSideEffect, inferFlavor(CGM, S), mlir::ArrayAttr());
 
   if (false /*IsGCCAsmGoto*/) {
-    assert(!MissingFeatures::asmGoto());
+    assert(!cir::MissingFeatures::asmGoto());
   } else if (HasUnwindClobber) {
-    assert(!MissingFeatures::asmUnwindClobber());
+    assert(!cir::MissingFeatures::asmUnwindClobber());
   } else {
-    assert(!MissingFeatures::asmMemoryEffects());
+    assert(!cir::MissingFeatures::asmMemoryEffects());
 
     mlir::Value result;
     if (IA.getNumResults())

clang/lib/CIR/CodeGen/CIRGenAtomic.cpp

@@ -30,8 +30,8 @@
 #include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Value.h"
 
-using namespace cir;
 using namespace clang;
+using namespace clang::CIRGen;
 
 namespace {
 class AtomicInfo {
@@ -42,7 +42,7 @@ class AtomicInfo {
   uint64_t ValueSizeInBits;
   CharUnits AtomicAlign;
   CharUnits ValueAlign;
-  TypeEvaluationKind EvaluationKind;
+  cir::TypeEvaluationKind EvaluationKind;
   bool UseLibcall;
   LValue LVal;
   CIRGenBitFieldInfo BFI;
@@ -51,7 +51,7 @@ class AtomicInfo {
 public:
   AtomicInfo(CIRGenFunction &CGF, LValue &lvalue, mlir::Location l)
       : CGF(CGF), AtomicSizeInBits(0), ValueSizeInBits(0),
-        EvaluationKind(TEK_Scalar), UseLibcall(true), loc(l) {
+        EvaluationKind(cir::TEK_Scalar), UseLibcall(true), loc(l) {
     assert(!lvalue.isGlobalReg());
     ASTContext &C = CGF.getContext();
     if (lvalue.isSimple()) {
@@ -102,7 +102,7 @@ class AtomicInfo {
   CharUnits getAtomicAlignment() const { return AtomicAlign; }
   uint64_t getAtomicSizeInBits() const { return AtomicSizeInBits; }
   uint64_t getValueSizeInBits() const { return ValueSizeInBits; }
-  TypeEvaluationKind getEvaluationKind() const { return EvaluationKind; }
+  cir::TypeEvaluationKind getEvaluationKind() const { return EvaluationKind; }
   bool shouldUseLibcall() const { return UseLibcall; }
   const LValue &getAtomicLValue() const { return LVal; }
   mlir::Value getAtomicPointer() const {
@@ -287,13 +287,13 @@ bool AtomicInfo::requiresMemSetZero(mlir::Type ty) const {
   switch (getEvaluationKind()) {
   // For scalars and complexes, check whether the store size of the
   // type uses the full size.
-  case TEK_Scalar:
+  case cir::TEK_Scalar:
     return !isFullSizeType(CGF.CGM, ty, AtomicSizeInBits);
-  case TEK_Complex:
+  case cir::TEK_Complex:
     llvm_unreachable("NYI");
 
   // Padding in structs has an undefined bit pattern.  User beware.
-  case TEK_Aggregate:
+  case cir::TEK_Aggregate:
     return false;
   }
   llvm_unreachable("bad evaluation kind");
@@ -545,7 +545,7 @@ static void buildAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
                           mlir::Value IsWeak, mlir::Value FailureOrder,
                           uint64_t Size, mlir::cir::MemOrder Order,
                           uint8_t Scope) {
-  assert(!MissingFeatures::syncScopeID());
+  assert(!cir::MissingFeatures::syncScopeID());
   StringRef Op;
 
   auto &builder = CGF.getBuilder();
@@ -592,7 +592,7 @@ static void buildAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
   case AtomicExpr::AO__scoped_atomic_load: {
     auto *load = builder.createLoad(loc, Ptr).getDefiningOp();
     // FIXME(cir): add scope information.
-    assert(!MissingFeatures::syncScopeID());
+    assert(!cir::MissingFeatures::syncScopeID());
     load->setAttr("mem_order", orderAttr);
     if (E->isVolatile())
       load->setAttr("is_volatile", mlir::UnitAttr::get(builder.getContext()));
@@ -618,7 +618,7 @@ static void buildAtomicOp(CIRGenFunction &CGF, AtomicExpr *E, Address Dest,
   case AtomicExpr::AO__scoped_atomic_store_n: {
     auto loadVal1 = builder.createLoad(loc, Val1);
     // FIXME(cir): add scope information.
-    assert(!MissingFeatures::syncScopeID());
+    assert(!cir::MissingFeatures::syncScopeID());
     builder.createStore(loc, loadVal1, Ptr, E->isVolatile(),
                         /*alignment=*/mlir::IntegerAttr{}, orderAttr);
     return;
@@ -791,15 +791,15 @@ static void buildAtomicOp(CIRGenFunction &CGF, AtomicExpr *Expr, Address Dest,
   // LLVM atomic instructions always have synch scope. If clang atomic
   // expression has no scope operand, use default LLVM synch scope.
   if (!ScopeModel) {
-    assert(!MissingFeatures::syncScopeID());
+    assert(!cir::MissingFeatures::syncScopeID());
     buildAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
                   Order, /*FIXME(cir): LLVM default scope*/ 1);
     return;
   }
 
   // Handle constant scope.
   if (getConstOpIntAttr(Scope)) {
-    assert(!MissingFeatures::syncScopeID());
+    assert(!cir::MissingFeatures::syncScopeID());
     llvm_unreachable("NYI");
     return;
   }
@@ -1469,7 +1469,7 @@ void CIRGenFunction::buildAtomicStore(RValue rvalue, LValue dest,
       store.setIsVolatile(true);
 
     // DecorateInstructionWithTBAA
-    assert(!MissingFeatures::tbaa());
+    assert(!cir::MissingFeatures::tbaa());
     return;
   }
 
@@ -1480,18 +1480,18 @@ void CIRGenFunction::buildAtomicInit(Expr *init, LValue dest) {
   AtomicInfo atomics(*this, dest, getLoc(init->getSourceRange()));
 
   switch (atomics.getEvaluationKind()) {
-  case TEK_Scalar: {
+  case cir::TEK_Scalar: {
     mlir::Value value = buildScalarExpr(init);
     atomics.emitCopyIntoMemory(RValue::get(value));
     return;
   }
 
-  case TEK_Complex: {
+  case cir::TEK_Complex: {
     llvm_unreachable("NYI");
     return;
   }
 
-  case TEK_Aggregate: {
+  case cir::TEK_Aggregate: {
     // Fix up the destination if the initializer isn't an expression
     // of atomic type.
     llvm_unreachable("NYI");

clang/lib/CIR/CodeGen/CIRGenBuilder.cpp

@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 #include "CIRGenBuilder.h"
 
-namespace cir {
+using namespace clang::CIRGen;
 
 mlir::Value CIRGenBuilderTy::maybeBuildArrayDecay(mlir::Location loc,
                                                   mlir::Value arrayPtr,
@@ -67,4 +67,3 @@ mlir::cir::ConstantOp CIRGenBuilderTy::getConstInt(mlir::Location loc,
   return create<mlir::cir::ConstantOp>(loc, intTy,
                                        mlir::cir::IntAttr::get(t, C));
 }
-} // namespace cir