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[LowertoHW] Lower NonLocalAnchor symbols with the VerbatimOp #2015

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prithayan
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Add support to use NonLocalAnchor with VerbatimOps to lower any FIRRTL op to the corresponding symbol in hw dialect.

TODO:

  • Extend support to all operations other than MemOp
  • Add support for hierarchical names
  • Add more integration test cases

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I'm not a competent reviewer for this, but it is a big design smell in the emitter for per-module emission stuff to go mutate global state (even with the mutex).

Is there something somewhere that describes the design of firrtl.nla? I don't understand what it is trying to do here. @darthscsi do you have thoughts here?


if (nlaAnno)
if (auto nla = nlaAnno.get("circt.nonlocal"))
if (auto sym = nla.dyn_cast_or_null<FlatSymbolRefAttr>()) {
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dyn_cast_or_null -> dyn_cast since you check for null in the previous if.

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I'm not a competent reviewer for this, but it is a big design smell in the emitter for per-module emission stuff to go mutate global state (even with the mutex).

Is there something somewhere that describes the design of firrtl.nla? I don't understand what it is trying to do here. @darthscsi do you have thoughts here?

I added some documentation for the firrtl.nla (https://github.com/llvm/circt/blob/main/docs/RationaleFIRRTL.md#nonlocalanchor)

I think we can avoid the global state update, working on that next.

The main objective here is to be able to use the Verilog name of FIRRTL objects without attaching symbols with them.
NLAs can define a symbol and identify any named object inside a module.
This PR is required to lower the firrtl.nla to the appropriate symbol in the sv dialect.
For example, given firrtl.nla @nla_1 [@Bar] ["w1"] , if w1 is a wire in module Bar, then the symbol @nla_1 can be replaced with the symbol defined by the sv.wire after lowering.
The lowering also depends on the how everything is named in HW dialect, which Andrew is currently working on.

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Closing this, created a new PR to implement it, #2050

@prithayan prithayan closed this Oct 28, 2021
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