diff --git a/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp b/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp
index 734fd602972d..f3593b6a538c 100644
--- a/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp
+++ b/lib/Dialect/SV/Transforms/SVExtractTestCode.cpp
@@ -22,8 +22,10 @@
 #include "circt/Dialect/SV/SVPasses.h"
 #include "circt/Dialect/Seq/SeqDialect.h"
 #include "circt/Dialect/Seq/SeqOps.h"
+#include "circt/Support/Namespace.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/IRMapping.h"
+#include "llvm/ADT/SetVector.h"
 
 #include <set>
 
@@ -202,12 +204,15 @@ static hw::HWModuleOp createModuleForCut(hw::HWModuleOp op,
   // Construct the ports, this is just the input Values
   SmallVector<hw::PortInfo> ports;
   {
+    Namespace portNames;
     auto srcPorts = op.getInputNames();
     for (auto port : llvm::enumerate(realInputs)) {
-      auto name = getNameForPort(port.value(), srcPorts);
-      ports.push_back(
-          {{name, port.value().getType(), hw::ModulePort::Direction::Input},
-           port.index()});
+      auto name = getNameForPort(port.value(), srcPorts).getValue();
+      name = portNames.newName(name.empty() ? "port_" + Twine(port.index())
+                                            : name);
+      ports.push_back({{b.getStringAttr(name), port.value().getType(),
+                        hw::ModulePort::Direction::Input},
+                       port.index()});
     }
   }
 
diff --git a/test/Dialect/SV/hw-extract-test-code.mlir b/test/Dialect/SV/hw-extract-test-code.mlir
index 32130ea9f7c6..b351dc384189 100644
--- a/test/Dialect/SV/hw-extract-test-code.mlir
+++ b/test/Dialect/SV/hw-extract-test-code.mlir
@@ -552,3 +552,26 @@ module {
     hw.output
   }
 }
+
+
+// -----
+
+// Check that no anonymous ports are created and all the port names are unique.
+
+module {
+  hw.module @PortName(in %clock : !seq.clock, in %in : i1) {
+    %x = hw.instance "pF" @PortNameFoo(clock: %clock: !seq.clock, "": %in: i1) -> (o: i1)
+    hw.output
+  }
+  // CHECK-LABEL: hw.module @PortNameFoo_cover
+  // CHECK-SAME: (in %clock : !seq.clock, in %port_1 : i1, in %port_2 : i1)
+  hw.module private @PortNameFoo(in %clock: !seq.clock, in %1: i1, out o : i1) {
+    // CHECK: hw.instance "PortNameFoo_cover"
+    // CHECK-SAME: @PortNameFoo_cover(clock: %clock: !seq.clock, port_1: %arg0: i1, port_2: %0: i1) -> ()
+    %0 = seq.from_clock %clock
+    %2 = comb.xor %1, %1 : i1
+    sv.cover.concurrent posedge %0, %1 label "cover__hello1"
+    sv.cover.concurrent posedge %0, %2 label "cover__hello2"
+    hw.output %2 : i1
+  }
+}