From b6f50d69e5897324c8dd25cb8ed19235d5564f61 Mon Sep 17 00:00:00 2001
From: Will Dietz <will.dietz@sifive.com>
Date: Thu, 14 Mar 2024 09:48:58 -0500
Subject: [PATCH] [FIRRTL][LowerAnnotations] Fix non-probe type compat check.
 (#6822)

Compatibility dest/source operands were backwards,
introduced in #4656 .

Add test as "legacy wiring" as non-ref-type-port path is a hidden option.

Fixes #6819.
---
 .../FIRRTL/Transforms/LowerAnnotations.cpp    |  2 +-
 test/Dialect/FIRRTL/legacy-wiring.mlir        | 29 +++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
index 6e42f32c401f..395e2016e3d4 100644
--- a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
+++ b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp
@@ -858,7 +858,7 @@ LogicalResult LowerAnnotationsPass::solveWiringProblems(ApplyState &state) {
       // Otherwise they must be identical or FIRRTL type-equivalent
       // (connectable).
       if (sourceFType != sinkFType &&
-          !areTypesEquivalent(sourceFType, sinkFType)) {
+          !areTypesEquivalent(sinkFType, sourceFType)) {
         auto diag = mlir::emitError(source.getLoc())
                     << "Wiring Problem source type " << sourceType
                     << " does not match sink type " << sinkType;
diff --git a/test/Dialect/FIRRTL/legacy-wiring.mlir b/test/Dialect/FIRRTL/legacy-wiring.mlir
index d5b555084ab3..2d1932901532 100644
--- a/test/Dialect/FIRRTL/legacy-wiring.mlir
+++ b/test/Dialect/FIRRTL/legacy-wiring.mlir
@@ -206,3 +206,32 @@ firrtl.circuit "IntWidths" attributes {
     firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
   }
 }
+
+// -----
+
+// Check direction of compatibility using const/non-const issue encountered (#6819).
+firrtl.circuit "Issue6819" attributes {
+ rawAnnotations = [
+  {
+    class = "firrtl.passes.wiring.SourceAnnotation",
+    target = "~Issue6819|Bar>y",
+    pin = "xyz"
+  },
+  {
+    class = "firrtl.passes.wiring.SinkAnnotation",
+    target = "~Issue6819|Issue6819>x",
+    pin = "xyz"
+  }
+  ]} {
+  firrtl.module private @Bar() {
+    %y = firrtl.wire interesting_name : !firrtl.const.uint<4>
+  }
+  // CHECK-LABEL: module @Issue6819
+  firrtl.module @Issue6819() {
+    // CHECK: firrtl.connect %x, %{{[^ ]*}} : !firrtl.uint, !firrtl.const.uint<4>
+    firrtl.instance bar interesting_name @Bar()
+    %x = firrtl.wire interesting_name : !firrtl.uint
+    %invalid_ui1 = firrtl.invalidvalue : !firrtl.uint
+    firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint
+  }
+}