diff --git a/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp b/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp
index 3eea1df5e3d8..7d24c59ba524 100644
--- a/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp
+++ b/lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp
@@ -1334,6 +1334,10 @@ bool TypeLoweringVisitor::visitExpr(mlir::UnrealizedConversionCastOp op) {
     return builder->create<mlir::UnrealizedConversionCastOp>(field.type, input)
         .getResult(0);
   };
+  // If the input to the cast is not a FIRRTL type, getSubWhatever cannot handle
+  // it, donot lower the op.
+  if (!type_isa<FIRRTLType>(op->getOperand(0).getType()))
+    return false;
   return lowerProducer(op, clone);
 }
 
diff --git a/test/Dialect/FIRRTL/lower-types.mlir b/test/Dialect/FIRRTL/lower-types.mlir
index d00649955d8e..0b98d0451020 100644
--- a/test/Dialect/FIRRTL/lower-types.mlir
+++ b/test/Dialect/FIRRTL/lower-types.mlir
@@ -1,5 +1,5 @@
-// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-types))' %s | FileCheck --check-prefixes=CHECK,COMMON %s
-// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-types{preserve-aggregate=all}))' %s | FileCheck --check-prefixes=AGGREGATE,COMMON %s
+// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-types))' --allow-unregistered-dialect %s | FileCheck --check-prefixes=CHECK,COMMON %s
+// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-types{preserve-aggregate=all}))' --allow-unregistered-dialect %s | FileCheck --check-prefixes=AGGREGATE,COMMON %s
 
 
 firrtl.circuit "TopLevel" {
@@ -1363,4 +1363,12 @@ firrtl.circuit "WireProbe" {
     firrtl.ref.define %y, %sp_y : !firrtl.probe<uint<5>>
     firrtl.ref.define %z, %sp_z : !firrtl.probe<uint<5>>
   }
+  firrtl.module @UnrealizedConversion( ){
+    // CHECK: %[[a:.+]] = "d.w"() : () -> !hw.struct<data: i64, tag: i1>
+    // CHECK: = builtin.unrealized_conversion_cast %[[a]] : !hw.struct<data: i64, tag: i1> to !firrtl.bundle<data: uint<64>, tag: uint<1>>
+    %a = "d.w"() : () -> (!hw.struct<data: i64, tag: i1>)
+    %b = builtin.unrealized_conversion_cast %a : !hw.struct<data: i64, tag: i1> to !firrtl.bundle<data: uint<64>, tag: uint<1>>
+    %w = firrtl.wire : !firrtl.bundle<data: uint<64>, tag: uint<1>>
+    firrtl.strictconnect %w, %b : !firrtl.bundle<data: uint<64>, tag: uint<1>>
+  }
 }