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Revert "AMDGPU: Add VI i16 support"
This reverts commit r285939 and r285948. These broke some conformance tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285995 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 1228c39 commit ae152bd

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‎lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -493,8 +493,6 @@ def isCIVI : Predicate <
493493

494494
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
495495

496-
def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">;
497-
498496
class PredicateControl {
499497
Predicate SubtargetPredicate;
500498
Predicate SIAssemblerPredicate = isSICI;

‎lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 3 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -586,32 +586,19 @@ bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const
586586

587587
bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
588588
// Truncate is just accessing a subregister.
589-
590-
unsigned SrcSize = Source.getSizeInBits();
591-
unsigned DestSize = Dest.getSizeInBits();
592-
593-
return DestSize < SrcSize && DestSize % 32 == 0 ;
589+
return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
594590
}
595591

596592
bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
597593
// Truncate is just accessing a subregister.
598-
599-
unsigned SrcSize = Source->getScalarSizeInBits();
600-
unsigned DestSize = Dest->getScalarSizeInBits();
601-
602-
if (DestSize== 16 && Subtarget->has16BitInsts())
603-
return SrcSize >= 32;
604-
605-
return DestSize < SrcSize && DestSize % 32 == 0;
594+
return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
595+
(Dest->getPrimitiveSizeInBits() % 32 == 0);
606596
}
607597

608598
bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
609599
unsigned SrcSize = Src->getScalarSizeInBits();
610600
unsigned DestSize = Dest->getScalarSizeInBits();
611601

612-
if (SrcSize == 16 && Subtarget->has16BitInsts())
613-
return DestSize >= 32;
614-
615602
return SrcSize == 32 && DestSize == 64;
616603
}
617604

@@ -620,10 +607,6 @@ bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
620607
// practical purposes, the extra mov 0 to load a 64-bit is free. As used,
621608
// this will enable reducing 64-bit operations the 32-bit, which is always
622609
// good.
623-
624-
if (Src == MVT::i16)
625-
return Dest == MVT::i32 ||Dest == MVT::i64 ;
626-
627610
return Src == MVT::i32 && Dest == MVT::i64;
628611
}
629612

@@ -2463,10 +2446,6 @@ SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
24632446
if (VT.isVector() || Size > 64)
24642447
return SDValue();
24652448

2466-
// There are i16 integer mul/mad.
2467-
if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16))
2468-
return SDValue();
2469-
24702449
SelectionDAG &DAG = DCI.DAG;
24712450
SDLoc DL(N);
24722451

‎lib/Target/AMDGPU/AMDGPUInstructions.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -529,14 +529,14 @@ multiclass BFIPatterns <Instruction BFI_INT,
529529

530530
def : Pat <
531531
(fcopysign f32:$src0, f32:$src1),
532-
(BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0, $src1)
532+
(BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
533533
>;
534534

535535
def : Pat <
536536
(f64 (fcopysign f64:$src0, f64:$src1)),
537537
(REG_SEQUENCE RC64,
538538
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
539-
(BFI_INT (LoadImm32 (i32 0x7fffffff)),
539+
(BFI_INT (LoadImm32 0x7fffffff),
540540
(i32 (EXTRACT_SUBREG $src0, sub1)),
541541
(i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
542542
>;
@@ -545,7 +545,7 @@ multiclass BFIPatterns <Instruction BFI_INT,
545545
(f64 (fcopysign f64:$src0, f32:$src1)),
546546
(REG_SEQUENCE RC64,
547547
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
548-
(BFI_INT (LoadImm32 (i32 0x7fffffff)),
548+
(BFI_INT (LoadImm32 0x7fffffff),
549549
(i32 (EXTRACT_SUBREG $src0, sub1)),
550550
$src1), sub1)
551551
>;

‎lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 7 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -708,13 +708,13 @@ let Predicates = [isGCN] in {
708708
// int_SI_vs_load_input
709709
def : Pat<
710710
(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
711-
(BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, (i32 0), imm:$attr_offset, 0, 0, 0)
711+
(BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0)
712712
>;
713713

714714
// Offset in an 32-bit VGPR
715715
def : Pat <
716716
(SIload_constant v4i32:$sbase, i32:$voff),
717-
(BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, (i32 0), 0, 0, 0, 0)
717+
(BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0)
718718
>;
719719

720720

@@ -914,7 +914,7 @@ def : Pat<
914914
>;
915915

916916

917-
class MUBUFLoad_PatternADDR64 <MUBUF_Pseudo Instr_ADDR64, ValueType vt,
917+
class MUBUFLoad_Pattern <MUBUF_Pseudo Instr_ADDR64, ValueType vt,
918918
PatFrag constant_ld> : Pat <
919919
(vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
920920
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
@@ -936,34 +936,15 @@ multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Ins
936936
}
937937

938938
let Predicates = [isSICI] in {
939-
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
940-
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
941-
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
942-
def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
939+
def : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
940+
def : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
941+
def : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
942+
def : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
943943

944944
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>;
945945
defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>;
946946
} // End Predicates = [isSICI]
947947

948-
multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
949-
PatFrag ld> {
950-
951-
def : Pat <
952-
(vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset,
953-
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
954-
(Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe)
955-
>;
956-
}
957-
958-
let Predicates = [Has16BitInsts] in {
959-
960-
defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, sextloadi8_constant>;
961-
defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, az_extloadi8_constant>;
962-
defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_OFFSET, i16, mubuf_sextloadi8>;
963-
defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_OFFSET, i16, mubuf_az_extloadi8>;
964-
965-
} // End Predicates = [Has16BitInsts]
966-
967948
class MUBUFScratchLoadPat <MUBUF_Pseudo Instr, ValueType vt, PatFrag ld> : Pat <
968949
(vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
969950
i32:$soffset, u16imm:$offset))),
@@ -972,8 +953,6 @@ class MUBUFScratchLoadPat <MUBUF_Pseudo Instr, ValueType vt, PatFrag ld> : Pat <
972953

973954
def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
974955
def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
975-
def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i16, sextloadi8_private>;
976-
def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i16, extloadi8_private>;
977956
def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
978957
def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
979958
def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
@@ -1046,20 +1025,6 @@ defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_
10461025
defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, global_store_atomic>;
10471026
} // End Predicates = [isSICI]
10481027

1049-
1050-
multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt,
1051-
PatFrag st> {
1052-
1053-
def : Pat <
1054-
(st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1055-
i16:$offset, i1:$glc, i1:$slc, i1:$tfe)),
1056-
(Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
1057-
>;
1058-
}
1059-
1060-
defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE_OFFSET, i16, truncstorei8_global>;
1061-
defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT_OFFSET, i16, global_store>;
1062-
10631028
class MUBUFScratchStorePat <MUBUF_Pseudo Instr, ValueType vt, PatFrag st> : Pat <
10641029
(st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
10651030
u16imm:$offset)),
@@ -1068,8 +1033,6 @@ class MUBUFScratchStorePat <MUBUF_Pseudo Instr, ValueType vt, PatFrag st> : Pat
10681033

10691034
def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
10701035
def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
1071-
def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i16, truncstorei8_private>;
1072-
def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i16, store_private>;
10731036
def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
10741037
def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
10751038
def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;

‎lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -489,12 +489,8 @@ class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
489489

490490
def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
491491
def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
492-
def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
493-
def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
494-
def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
495492
def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
496493
def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
497-
def : DSReadPat <DS_READ_U16, i16, si_load_local>;
498494
def : DSReadPat <DS_READ_B32, i32, si_load_local>;
499495

500496
let AddedComplexity = 100 in {
@@ -516,8 +512,6 @@ class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
516512

517513
def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
518514
def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
519-
def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
520-
def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
521515
def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
522516

523517
let AddedComplexity = 100 in {
@@ -528,8 +522,8 @@ def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
528522
def : Pat <
529523
(si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
530524
i8:$offset1)),
531-
(DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
532-
(i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
525+
(DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0),
526+
(EXTRACT_SUBREG $value, sub1), $offset0, $offset1,
533527
(i1 0))
534528
>;
535529

‎lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -341,8 +341,6 @@ let Predicates = [isCIVI] in {
341341

342342
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
343343
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
344-
def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
345-
def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
346344
def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
347345
def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
348346
def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
@@ -391,10 +389,6 @@ def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
391389

392390
} // End Predicates = [isCIVI]
393391

394-
let Predicates = [isVI] in {
395-
def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei8, i16>;
396-
def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
397-
}
398392

399393

400394
//===----------------------------------------------------------------------===//

‎lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 4 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -78,9 +78,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
7878
addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
7979
addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
8080

81-
if (Subtarget->has16BitInsts())
82-
addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
83-
8481
computeRegisterProperties(STI.getRegisterInfo());
8582

8683
// We need to custom lower vector stores from local memory
@@ -224,55 +221,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
224221
setOperationAction(ISD::FDIV, MVT::f32, Custom);
225222
setOperationAction(ISD::FDIV, MVT::f64, Custom);
226223

227-
if (Subtarget->has16BitInsts()) {
228-
setOperationAction(ISD::Constant, MVT::i16, Legal);
229-
230-
setOperationAction(ISD::SMIN, MVT::i16, Legal);
231-
setOperationAction(ISD::SMAX, MVT::i16, Legal);
232-
233-
setOperationAction(ISD::UMIN, MVT::i16, Legal);
234-
setOperationAction(ISD::UMAX, MVT::i16, Legal);
235-
236-
setOperationAction(ISD::SETCC, MVT::i16, Promote);
237-
AddPromotedToType(ISD::SETCC, MVT::i16, MVT::i32);
238-
239-
setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
240-
AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
241-
242-
setOperationAction(ISD::ROTR, MVT::i16, Promote);
243-
setOperationAction(ISD::ROTL, MVT::i16, Promote);
244-
245-
setOperationAction(ISD::SDIV, MVT::i16, Promote);
246-
setOperationAction(ISD::UDIV, MVT::i16, Promote);
247-
setOperationAction(ISD::SREM, MVT::i16, Promote);
248-
setOperationAction(ISD::UREM, MVT::i16, Promote);
249-
250-
setOperationAction(ISD::BSWAP, MVT::i16, Promote);
251-
setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
252-
253-
setOperationAction(ISD::CTTZ, MVT::i16, Promote);
254-
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
255-
setOperationAction(ISD::CTLZ, MVT::i16, Promote);
256-
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
257-
258-
setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
259-
260-
setOperationAction(ISD::BR_CC, MVT::i16, Expand);
261-
262-
setOperationAction(ISD::LOAD, MVT::i16, Custom);
263-
264-
setTruncStoreAction(MVT::i64, MVT::i16, Expand);
265-
266-
setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
267-
AddPromotedToType(ISD::UINT_TO_FP, MVT::i16, MVT::i32);
268-
setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
269-
AddPromotedToType(ISD::SINT_TO_FP, MVT::i16, MVT::i32);
270-
setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
271-
AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
272-
setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
273-
AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
274-
}
275-
276224
setTargetDAGCombine(ISD::FADD);
277225
setTargetDAGCombine(ISD::FSUB);
278226
setTargetDAGCombine(ISD::FMINNUM);
@@ -2610,17 +2558,16 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
26102558
EVT MemVT = Load->getMemoryVT();
26112559

26122560
if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
2561+
assert(MemVT == MVT::i1 && "Only i1 non-extloads expected");
26132562
// FIXME: Copied from PPC
26142563
// First, load into 32 bits, then truncate to 1 bit.
26152564

26162565
SDValue Chain = Load->getChain();
26172566
SDValue BasePtr = Load->getBasePtr();
26182567
MachineMemOperand *MMO = Load->getMemOperand();
26192568

2620-
EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
2621-
26222569
SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
2623-
BasePtr, RealMemVT, MMO);
2570+
BasePtr, MVT::i8, MMO);
26242571

26252572
SDValue Ops[] = {
26262573
DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD),
@@ -3434,23 +3381,8 @@ static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
34343381
}
34353382

34363383
EVT VT = K0->getValueType(0);
3437-
3438-
MVT NVT = MVT::i32;
3439-
unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3440-
3441-
SDValue Tmp1, Tmp2, Tmp3;
3442-
Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
3443-
Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
3444-
Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
3445-
3446-
if (VT == MVT::i16) {
3447-
Tmp1 = DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, NVT,
3448-
Tmp1, Tmp2, Tmp3);
3449-
3450-
return DAG.getNode(ISD::TRUNCATE, SL, VT, Tmp1);
3451-
} else
3452-
return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
3453-
Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
3384+
return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
3385+
Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
34543386
}
34553387

34563388
static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {

‎lib/Target/AMDGPU/SIInstrInfo.td‎

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@@ -1128,6 +1128,7 @@ def getAtomicNoRetOp : InstrMapping {
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include "SIInstructions.td"
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include "CIInstructions.td"
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include "VIInstructions.td"
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include "DSInstructions.td"
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include "MIMGInstructions.td"

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