update data generate

Author: liuwei9

py/dataGenerate.py

@@ -0,0 +1,53 @@
+import torch.nn as nn
+import torch
+import numpy as np
+import json
+import sys
+import paddingMode
+
+
+def dataGenerate(cfgPath, saveDataGenerateFile=True):
+    _, paddingData = paddingMode.padding(cfgPath, True)
+    with open(cfgPath) as f:
+        a = json.load(f)
+    dst_dataGenerate_py = a['featureGenerateSim']['dst_py']
+    dst_dataGenerate_scala = a['featureGenerateSim']['dst_scala']
+    computeChannel = a['total']['COMPUTE_CHANNEL_NUM']
+    KERNEL_NUM = a['featureGeneratePara']['KERNEL_NUM']
+    FEATURE_RAM_ADDR_WIDTH = a['featureGeneratePara']['FEATURE_RAM_ADDR_WIDTH']
+
+    h = paddingData.shape[1]
+    w = paddingData.shape[2]
+    c = paddingData.shape[0]
+    d = []
+    d.append(paddingData[:, 0:h - 2, 0:w - 2])
+    d.append(paddingData[:, 0:h - 2, 1:w - 1])
+    d.append(paddingData[:, 0:h - 2, 2:w])
+    d.append(paddingData[:, 1:h - 1, 0:w - 2])
+    d.append(paddingData[:, 1:h - 1, 1:w - 1])
+    d.append(paddingData[:, 1:h - 1, 2:w])
+    d.append(paddingData[:, 2:h, 0:w - 2])
+    d.append(paddingData[:, 2:h, 1:w - 1])
+    d.append(paddingData[:, 2:h, 2:w])
+    for i in range(9):
+        fp = open(dst_dataGenerate_py + "d" + str(i)+".txt", 'w')
+
+        def save_xx(high, width, channel, xx, fp):
+            for i in range(high):
+                for j in range(width):
+                    out = []
+                    for k in range(channel):
+                        out.append(xx[k][i][j])
+                        if len(out) == computeChannel:
+                            out.reverse()
+                            for m in out:
+                                m = m.item()
+                                fp.write('%02x' % m)
+                            fp.write('\n')
+                            out = []
+            fp.close()
+
+        save_xx(h - 2, w - 2, c, d[i], fp)
+
+
+dataGenerate("../simData/config.json", False)

py/paddingMode.py

@@ -5,18 +5,18 @@
 import sys
 
 
-def main(cfgPath):
+def padding(cfgPath, saveFile=True):
     with open(cfgPath) as f:
         a = json.load(f)
-    channel = a['padding']['channelIn']
-    row = a['padding']['rowNumIn']
-    col = a['padding']['colNumIn']
-    enPadding = a['padding']['enPadding']
-    src = a['padding']['src_py']
-    dst = a['padding']['dst_py']
-    computeChannel = a['padding']['COMPUTE_CHANNEL_NUM']
-    zeroData = a['padding']['zeroDara']
-    zeroNum = a['padding']['zeroNum']
+    channel = a['paddingSim']['channelIn']
+    row = a['paddingSim']['rowNumIn']
+    col = a['paddingSim']['colNumIn']
+    enPadding = a['paddingSim']['enPadding']
+    src = a['paddingSim']['src_py']
+    dst = a['paddingSim']['dst_py']
+    computeChannel = a['total']['COMPUTE_CHANNEL_NUM']
+    zeroData = a['paddingSim']['zeroDara']
+    zeroNum = a['paddingSim']['zeroNum']
 
     x = torch.randint(0, 127, (channel, row, col))
     xx = np.array(x)
@@ -25,28 +25,30 @@ def main(cfgPath):
         pad = nn.ConstantPad2d(padding=(zeroNum, zeroNum, zeroNum, zeroNum), value=zeroData)
         y = pad(x)
     yy = np.array(y)
-    fp1 = open(src, 'w')
-    fp2 = open(dst, 'w')
+    if (saveFile):
+        fp1 = open(src, 'w')
+        fp2 = open(dst, 'w')
 
-    def save_xx(high, width, channel, xx, fp):
-        out = []
-        for h in range(high):
-            for w in range(width):
-                for c in range(channel):
-                    out.append(xx[c][h][w])
-                    if len(out) == computeChannel:
-                        out.reverse()
-                        for m in out:
-                            m = m.item()
-                            fp.write('%02x' % m)
-                        fp.write('\n')
-                        out = []
-        fp.close()
+        def save_xx(high, width, channel, xx, fp):
+            out = []
+            for h in range(high):
+                for w in range(width):
+                    for c in range(channel):
+                        out.append(xx[c][h][w])
+                        if len(out) == computeChannel:
+                            out.reverse()
+                            for m in out:
+                                m = m.item()
+                                fp.write('%02x' % m)
+                            fp.write('\n')
+                            out = []
+            fp.close()
 
-    save_xx(xx.shape[1], xx.shape[2], xx.shape[0], xx, fp1)
-    save_xx(yy.shape[1], yy.shape[2], yy.shape[0], yy, fp2)
+        save_xx(xx.shape[1], xx.shape[2], xx.shape[0], xx, fp1)
+        save_xx(yy.shape[1], yy.shape[2], yy.shape[0], yy, fp2)
+    return [xx, yy]
 
 
 if __name__ == '__main__':
     # print(sys)
-    main("../simData/config.json")
+    padding("../simData/config.json")

py/simModule.py

@@ -1,17 +1,33 @@
 {
-  "padding": {
-    "enPadding": true,
-    "channelIn": 8,
-    "rowNumIn": 640,
-    "colNumIn": 320,
-    "zeroDara": 8,
-    "zeroNum": 2,
+  "total": {
     "COMPUTE_CHANNEL_NUM": 8,
     "DATA_WIDTH": 8,
     "CHANNEL_WIDTH": 10,
-    "FEATURE_WIDTH": 11,
-    "src_py": "G:/SpinalStudy/simData/src.txt",
-    "dst_py": "G:/SpinalStudy/simData/dst.txt",
-    "dst_scala": "G:/SpinalStudy/simData/dst_scala.txt"
+    "FEATURE_WIDTH": 11
+  },
+  "paddingPara": {
+
+  },
+  "paddingSim": {
+    "enPadding": true,
+    "channelIn": 16,
+    "rowNumIn": 320,
+    "colNumIn": 640,
+    "zeroDara": 8,
+    "zeroNum": 2,
+    "src_py": "G:/SpinalStudy/simData/src_padding.txt",
+    "dst_py": "G:/SpinalStudy/simData/dst_padding_py.txt",
+    "dst_scala": "G:/SpinalStudy/simData/dst_padding_scala.txt"
+  },
+  "featureGeneratePara": {
+    "KERNEL_NUM": 9,
+    "FEATURE_RAM_ADDR_WIDTH": 11
+  },
+  "featureGenerateSim": {
+    "dst_py": "G:/SpinalStudy/simData/dst_dataGenerate_py",
+    "dst_scala": "G:/SpinalStudy/simData/dst_dataGenerate_scala"
+  },
+  "simPath": {
+
   }
 }

simData/config.json

@@ -1,30 +1,27 @@
 import spinal.core._
 import spinal.lib.{master, slave}
-object FpgaDevice {
-    val vendor = "xilinx"
-    val A7 = "A7"
-    val K7 = "K7"
-    val V7="V7"
-    val VU="VU"
-    val KU="KU"
-    val ZYNQ = "ZYNQ"
 
-}
-case class DataGenerateConfig(DATA_WIDTH: Int, PICTURE_NUM: Int, CHANNEL_WIDTH: Int, COMPUTE_CHANNEL_NUM: Int, FEATURE_WIDTH: Int, KERNEL_NUM :Int,FEATURE_RAM_ADDR_WIDTH:Int,device: Device){
+
+case class DataGenerateConfig(DATA_WIDTH: Int,  CHANNEL_WIDTH: Int, COMPUTE_CHANNEL_NUM: Int, FEATURE_WIDTH: Int, KERNEL_NUM: Int, FEATURE_RAM_ADDR_WIDTH: Int, ZERO_NUM: Int) {
+    val PICTURE_NUM = 1
     val STREAM_DATA_WIDTH = DATA_WIDTH * PICTURE_NUM * COMPUTE_CHANNEL_NUM
-    val paddingConfig = PaddingConfig(DATA_WIDTH,PICTURE_NUM,CHANNEL_WIDTH,COMPUTE_CHANNEL_NUM,FEATURE_WIDTH)
-    val featureGenerateConfig = FeatureGenerateConfig(DATA_WIDTH,PICTURE_NUM,CHANNEL_WIDTH,COMPUTE_CHANNEL_NUM,FEATURE_WIDTH,KERNEL_NUM,FEATURE_RAM_ADDR_WIDTH,device: Device)
+    val paddingConfig = PaddingConfig(DATA_WIDTH, CHANNEL_WIDTH, COMPUTE_CHANNEL_NUM, FEATURE_WIDTH,ZERO_NUM)
+    val featureGenerateConfig = FeatureGenerateConfig(DATA_WIDTH,  CHANNEL_WIDTH, COMPUTE_CHANNEL_NUM, FEATURE_WIDTH, KERNEL_NUM, FEATURE_RAM_ADDR_WIDTH)
 }
+
 class DataGenerate(dataGenerateConfig: DataGenerateConfig) extends Component {
-    val io = new Bundle{
-        val sData = slave Stream(Bits(dataGenerateConfig.STREAM_DATA_WIDTH bits))
+    val io = new Bundle {
+        val sData = slave Stream (Bits(dataGenerateConfig.STREAM_DATA_WIDTH bits))
         val start = in Bool()
         val enPadding = in Bool()
         val channelIn = in UInt (dataGenerateConfig.CHANNEL_WIDTH bits)
         val rowNumIn = in UInt (dataGenerateConfig.FEATURE_WIDTH bits)
+        val colNumIn = in UInt(dataGenerateConfig.FEATURE_WIDTH bits)
         val zeroDara = in Bits (dataGenerateConfig.DATA_WIDTH bits)
         val zeroNum = in UInt (dataGenerateConfig.paddingConfig.ZERO_NUM_WIDTH bits)
-        val mData = master(FeaturePort(dataGenerateConfig.STREAM_DATA_WIDTH, dataGenerateConfig.KERNEL_NUM))
+        //        val mData = master(FeaturePort(dataGenerateConfig.STREAM_DATA_WIDTH, dataGenerateConfig.KERNEL_NUM))
+        val mData = Vec(master Stream Bits(dataGenerateConfig.STREAM_DATA_WIDTH bits), dataGenerateConfig.KERNEL_NUM)
+        val last = out Bool()
     }
     noIoPrefix()
     val padding = new Padding(dataGenerateConfig.paddingConfig)
@@ -33,17 +30,18 @@ class DataGenerate(dataGenerateConfig: DataGenerateConfig) extends Component {
     padding.io.enPadding <> io.enPadding
     padding.io.channelIn <> io.channelIn
     padding.io.rowNumIn <> io.rowNumIn
+    padding.io.colNumIn <> io.colNumIn
     padding.io.zeroNum <> io.zeroNum
     padding.io.zeroDara <> io.zeroDara
     val featureGenerate = new FeatureGenerate(dataGenerateConfig.featureGenerateConfig)
     featureGenerate.io.mData <> io.mData
     padding >> featureGenerate
+    featureGenerate.io.last <> io.last
 }
-object DataGenerate{
+
+object DataGenerate {
     def main(args: Array[String]): Unit = {
-        val  device = Device(vendor=FpgaDevice.vendor,family = FpgaDevice.K7)
         SpinalConfig(
-            device = device
-        ).generateVerilog(new DataGenerate(DataGenerateConfig(8,1,12,8,10,9,11,device)))
+        ).generateVerilog(new DataGenerate(DataGenerateConfig(8,  12, 8, 10, 9, 11, 1)))
     }
 }