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sh: Initial support for the MX-G CPU.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
1 parent b9e393c commit 2ad6990

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8 files changed

+194
-13
lines changed

8 files changed

+194
-13
lines changed

‎arch/sh/Kconfig

+9-2
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,12 @@ config CPU_SUBTYPE_SH7263
167167
select CPU_SH2A
168168
select CPU_HAS_FPU
169169

170+
config CPU_SUBTYPE_MXG
171+
bool "Support MX-G processor"
172+
select CPU_SH2A
173+
help
174+
Select MX-G if running on an R8A03022BG part.
175+
170176
# SH-3 Processor Support
171177

172178
config CPU_SUBTYPE_SH7705
@@ -560,7 +566,7 @@ config SH_TMU
560566
config SH_CMT
561567
def_bool y
562568
prompt "CMT timer support"
563-
depends on CPU_SH2
569+
depends on CPU_SH2 && !CPU_SUBTYPE_MXG
564570
help
565571
This enables the use of the CMT as the system timer.
566572

@@ -578,6 +584,7 @@ config SH_TIMER_IRQ
578584
default "86" if CPU_SUBTYPE_SH7619
579585
default "140" if CPU_SUBTYPE_SH7206
580586
default "142" if CPU_SUBTYPE_SH7203
587+
default "238" if CPU_SUBTYPE_MXG
581588
default "16"
582589

583590
config SH_PCLK_FREQ
@@ -588,7 +595,7 @@ config SH_PCLK_FREQ
588595
default "33333333" if CPU_SUBTYPE_SH7770 || \
589596
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
590597
CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
591-
CPU_SUBTYPE_SH7263
598+
CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
592599
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
593600
default "66000000" if CPU_SUBTYPE_SH4_202
594601
default "50000000"

‎arch/sh/Kconfig.debug

+7-6
Original file line numberDiff line numberDiff line change
@@ -29,16 +29,17 @@ config EARLY_SCIF_CONSOLE
2929
config EARLY_SCIF_CONSOLE_PORT
3030
hex
3131
depends on EARLY_SCIF_CONSOLE
32-
default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
33-
default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
34-
default "0xffea0000" if CPU_SUBTYPE_SH7785
35-
default "0xfffe8000" if CPU_SUBTYPE_SH7203
36-
default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
37-
default "0xf8420000" if CPU_SUBTYPE_SH7619
3832
default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
3933
default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
34+
default "0xf8420000" if CPU_SUBTYPE_SH7619
35+
default "0xff804000" if CPU_SUBTYPE_MXG
4036
default "0xffc30000" if CPU_SUBTYPE_SHX3
37+
default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
38+
CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
4139
default "0xffe80000" if CPU_SH4
40+
default "0xffea0000" if CPU_SUBTYPE_SH7785
41+
default "0xfffe8000" if CPU_SUBTYPE_SH7203
42+
default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
4243
default "0x00000000"
4344

4445
config EARLY_PRINTK

‎arch/sh/kernel/cpu/sh2a/Makefile

+4-3
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ common-y += $(addprefix ../sh2/, ex.o entry.o)
88

99
obj-$(CONFIG_SH_FPU) += fpu.o
1010

11-
obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
12-
obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13-
obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
11+
obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
12+
obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13+
obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
14+
obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o

‎arch/sh/kernel/cpu/sh2a/probe.c

+3
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,9 @@ int __init detect_cpu_and_cache_system(void)
2929
boot_cpu_data.type = CPU_SH7206;
3030
/* While SH7206 has a DSP.. */
3131
boot_cpu_data.flags |= CPU_HAS_DSP;
32+
#elif defined(CONFIG_CPU_SUBTYPE_MXG)
33+
boot_cpu_data.type = CPU_MXG;
34+
boot_cpu_data.flags |= CPU_HAS_DSP;
3235
#endif
3336

3437
boot_cpu_data.dcache.ways = 4;

‎arch/sh/kernel/cpu/sh2a/setup-mxg.c

+168
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,168 @@
1+
/*
2+
* Renesas MX-G (R8A03022BG) Setup
3+
*
4+
* Copyright (C) 2008 Paul Mundt
5+
*
6+
* This file is subject to the terms and conditions of the GNU General Public
7+
* License. See the file "COPYING" in the main directory of this archive
8+
* for more details.
9+
*/
10+
#include <linux/platform_device.h>
11+
#include <linux/init.h>
12+
#include <linux/serial.h>
13+
#include <linux/serial_sci.h>
14+
15+
enum {
16+
UNUSED = 0,
17+
18+
/* interrupt sources */
19+
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20+
IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
21+
22+
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23+
24+
SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
25+
26+
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
27+
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
28+
29+
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
30+
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
31+
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
32+
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
33+
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
34+
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
35+
MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
36+
37+
/* interrupt groups */
38+
PINT, SCIF0, SCIF1,
39+
MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
40+
};
41+
42+
static struct intc_vect vectors[] __initdata = {
43+
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
44+
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
45+
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
46+
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
47+
INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
48+
INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
49+
INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
50+
INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
51+
52+
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
53+
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
54+
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
55+
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
56+
57+
INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
58+
INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
59+
INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
60+
INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
61+
62+
INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
63+
INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
64+
INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
65+
INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
66+
67+
INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
68+
INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
69+
INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
70+
71+
INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
72+
INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
73+
INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
74+
75+
INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
76+
INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
77+
78+
INTC_IRQ(MTU2_TGI3B, 244),
79+
INTC_IRQ(MTU2_TGI3C, 245),
80+
81+
INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
82+
INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
83+
INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
84+
85+
INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
86+
INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
87+
};
88+
89+
static struct intc_group groups[] __initdata = {
90+
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
91+
PINT4, PINT5, PINT6, PINT7),
92+
INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
93+
MTU2_TCI0V, MTU2_TGI0E),
94+
INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
95+
MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
96+
INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
97+
MTU2_TGI3A),
98+
INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
99+
MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
100+
INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
101+
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
102+
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
103+
};
104+
105+
static struct intc_prio_reg prio_registers[] __initdata = {
106+
{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
107+
{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
108+
{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
109+
{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
110+
{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
111+
{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
112+
{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
113+
{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
114+
{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
115+
{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
116+
{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
117+
{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
118+
{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
119+
{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
120+
{ 0xfffd9812, 0, 16, 4, /* IPR15 */
121+
{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
122+
{ 0xfffd9814, 0, 16, 4, /* IPR16 */
123+
{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
124+
};
125+
126+
static struct intc_mask_reg mask_registers[] __initdata = {
127+
{ 0xfffd9408, 0, 16, /* PINTER */
128+
{ 0, 0, 0, 0, 0, 0, 0, 0,
129+
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
130+
};
131+
132+
static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
133+
mask_registers, prio_registers, NULL);
134+
135+
static struct plat_sci_port sci_platform_data[] = {
136+
{
137+
.mapbase = 0xff804000,
138+
.flags = UPF_BOOT_AUTOCONF,
139+
.type = PORT_SCIF,
140+
.irqs = { 223, 220, 221, 222 },
141+
}, {
142+
.flags = 0,
143+
}
144+
};
145+
146+
static struct platform_device sci_device = {
147+
.name = "sh-sci",
148+
.id = -1,
149+
.dev = {
150+
.platform_data = sci_platform_data,
151+
},
152+
};
153+
154+
static struct platform_device *mxg_devices[] __initdata = {
155+
&sci_device,
156+
};
157+
158+
static int __init mxg_devices_setup(void)
159+
{
160+
return platform_add_devices(mxg_devices,
161+
ARRAY_SIZE(mxg_devices));
162+
}
163+
__initcall(mxg_devices_setup);
164+
165+
void __init plat_irq_setup(void)
166+
{
167+
register_intc_controller(&intc_desc);
168+
}

‎arch/sh/kernel/setup.c

+1
Original file line numberDiff line numberDiff line change
@@ -335,6 +335,7 @@ static const char *cpu_name[] = {
335335
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
336336
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
337337
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
338+
[CPU_MXG] = "MX-G",
338339
[CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown"
339340
};
340341

‎include/asm-sh/bugs.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ static void __init check_bugs(void)
2525
case CPU_SH7619:
2626
*p++ = '2';
2727
break;
28-
case CPU_SH7203 ... CPU_SH7263:
28+
case CPU_SH7203 ... CPU_MXG:
2929
*p++ = '2';
3030
*p++ = 'a';
3131
break;

‎include/asm-sh/processor.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ enum cpu_type {
1616
CPU_SH7619,
1717

1818
/* SH-2A types */
19-
CPU_SH7203, CPU_SH7206, CPU_SH7263,
19+
CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
2020

2121
/* SH-3 types */
2222
CPU_SH7705, CPU_SH7706, CPU_SH7707,

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