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tiwaitiwai
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Merge branch 'for-next' into for-linus
Pull the 6.5-devel branch for upstreaming. Signed-off-by: Takashi Iwai <tiwai@suse.de>
2 parents e94f1f9 + 4e08713 commit a15b513

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‎Documentation/block/index.rst

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@@ -18,7 +18,6 @@ Block
1818
kyber-iosched
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null_blk
2020
pr
21-
request
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stat
2322
switching-sched
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writeback_cache_control

‎Documentation/block/request.rst

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This file was deleted.

‎Documentation/devicetree/bindings/media/i2c/ovti,ov2685.yaml

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@@ -49,6 +49,7 @@ properties:
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properties:
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data-lanes:
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minItems: 1
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maxItems: 2
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required:

‎Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml

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@@ -17,20 +17,11 @@ description:
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properties:
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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maxItems: 4
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clock-names:
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minItems: 3
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items:
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- const: pcie
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- const: pcie_bus
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- enum: [ pcie_phy, pcie_aux ]
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- enum: [ pcie_inbound_axi, pcie_aux ]
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maxItems: 4
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num-lanes:
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const: 1

‎Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

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@@ -31,6 +31,19 @@ properties:
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- const: dbi
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- const: addr_space
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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clock-names:
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minItems: 3
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maxItems: 4
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interrupts:
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items:
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- description: builtin eDMA interrupter.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_aux
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else:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_aux
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

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- const: dbi
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- const: config
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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clock-names:
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minItems: 3
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maxItems: 4
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interrupts:
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items:
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- description: builtin MSI controller.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx6sx-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_inbound_axi
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mq-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_aux
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_aux
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unevaluatedProperties: false
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‎Documentation/networking/bonding.rst

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@@ -776,10 +776,11 @@ peer_notif_delay
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Specify the delay, in milliseconds, between each peer
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notification (gratuitous ARP and unsolicited IPv6 Neighbor
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Advertisement) when they are issued after a failover event.
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This delay should be a multiple of the link monitor interval
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(arp_interval or miimon, whichever is active). The default
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value is 0 which means to match the value of the link monitor
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interval.
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This delay should be a multiple of the MII link monitor interval
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(miimon).
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The valid range is 0 - 300000. The default value is 0, which means
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to match the value of the MII link monitor interval.
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prio
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Slave priority. A higher number means higher priority.

‎Documentation/networking/index.rst

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udplite
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vrf
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vxlan
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x25-iface
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x25
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x25-iface
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xfrm_device
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xfrm_proc
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xfrm_sync

‎Documentation/networking/x25-iface.rst

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.. SPDX-License-Identifier: GPL-2.0
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3-
============================-
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X.25 Device Driver Interface
5-
============================-
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============================
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Version 1.1
87

‎Documentation/sound/cards/audigy-mixer.rst

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@@ -227,7 +227,7 @@ PCM stream related controls
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name='EMU10K1 PCM Volume',index 0-31
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------------------------------------
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Channel volume attenuation in range 0-0xffff. The maximum value (no
230+
Channel volume attenuation in range 0-0x1fffd. The middle value (no
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attenuation) is default. The channel mapping for three values is
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as follows:
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@@ -240,30 +240,30 @@ name='EMU10K1 PCM Send Routing',index 0-31
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This control specifies the destination - FX-bus accumulators. There are 24
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values in this mapping:
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243-
* 0 - mono, A destination (FX-bus 0-63), default 0
244-
* 1 - mono, B destination (FX-bus 0-63), default 1
245-
* 2 - mono, C destination (FX-bus 0-63), default 2
246-
* 3 - mono, D destination (FX-bus 0-63), default 3
247-
* 4 - mono, E destination (FX-bus 0-63), default 0
248-
* 5 - mono, F destination (FX-bus 0-63), default 0
249-
* 6 - mono, G destination (FX-bus 0-63), default 0
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* 7 - mono, H destination (FX-bus 0-63), default 0
251-
* 8 - left, A destination (FX-bus 0-63), default 0
252-
* 9 - left, B destination (FX-bus 0-63), default 1
243+
* 0 - mono, A destination (FX-bus 0-63), default 0
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* 1 - mono, B destination (FX-bus 0-63), default 1
245+
* 2 - mono, C destination (FX-bus 0-63), default 2
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* 3 - mono, D destination (FX-bus 0-63), default 3
247+
* 4 - mono, E destination (FX-bus 0-63), default 4
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* 5 - mono, F destination (FX-bus 0-63), default 5
249+
* 6 - mono, G destination (FX-bus 0-63), default 6
250+
* 7 - mono, H destination (FX-bus 0-63), default 7
251+
* 8 - left, A destination (FX-bus 0-63), default 0
252+
* 9 - left, B destination (FX-bus 0-63), default 1
253253
* 10 - left, C destination (FX-bus 0-63), default 2
254254
* 11 - left, D destination (FX-bus 0-63), default 3
255-
* 12 - left, E destination (FX-bus 0-63), default 0
256-
* 13 - left, F destination (FX-bus 0-63), default 0
257-
* 14 - left, G destination (FX-bus 0-63), default 0
258-
* 15 - left, H destination (FX-bus 0-63), default 0
255+
* 12 - left, E destination (FX-bus 0-63), default 4
256+
* 13 - left, F destination (FX-bus 0-63), default 5
257+
* 14 - left, G destination (FX-bus 0-63), default 6
258+
* 15 - left, H destination (FX-bus 0-63), default 7
259259
* 16 - right, A destination (FX-bus 0-63), default 0
260260
* 17 - right, B destination (FX-bus 0-63), default 1
261261
* 18 - right, C destination (FX-bus 0-63), default 2
262262
* 19 - right, D destination (FX-bus 0-63), default 3
263-
* 20 - right, E destination (FX-bus 0-63), default 0
264-
* 21 - right, F destination (FX-bus 0-63), default 0
265-
* 22 - right, G destination (FX-bus 0-63), default 0
266-
* 23 - right, H destination (FX-bus 0-63), default 0
263+
* 20 - right, E destination (FX-bus 0-63), default 4
264+
* 21 - right, F destination (FX-bus 0-63), default 5
265+
* 22 - right, G destination (FX-bus 0-63), default 6
266+
* 23 - right, H destination (FX-bus 0-63), default 7
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268268
Don't forget that it's illegal to assign a channel to the same FX-bus accumulator
269269
more than once (it means 0=0 && 1=0 is an invalid combination).

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