From f0e5fe97664bf493dfe050439038d7e9546f06a3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 Jul 2022 00:27:59 +0100 Subject: [PATCH 1/4] fel: add support for R528/T113s This SoC is using the same die as the RISC-V D1, but we don't support non-ARM yet. The memory map and peripherals (watchdog) are very similar to the V853, also the BROM enabled the instruction cache, so requires the same I cache hack. Signed-off-by: Andre Przywara --- soc_info.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/soc_info.c b/soc_info.c index 455f5cf10..d0af8ef8f 100644 --- a/soc_info.c +++ b/soc_info.c @@ -409,6 +409,18 @@ soc_info_t soc_info_table[] = { .sid_offset = 0x200, .icache_fix = true, .watchdog = &wd_v853_compat, + },{ + .soc_id = 0x1859, /* Allwinner D1/D1s/R528/T113-S3 */ + .name = "R528", + .spl_addr = 0x20000, + .scratch_addr = 0x21000, + .thunk_addr = 0x3a200, .thunk_size = 0x200, + .swap_buffers = v831_sram_swap_buffers, + .sram_size = 160 * 1024, + .sid_base = 0x03006000, + .sid_offset = 0x200, + .icache_fix = true, + .watchdog = &wd_v853_compat, },{ .swap_buffers = NULL /* End of the table */ } From 432e45d3d56ba815d53e34c0386ead8ce8888c9d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 28 Jul 2022 22:46:17 +0100 Subject: [PATCH 2/4] uart0-helloworld-sdboot: add R528/T113 support Clock and UART wise it's very similar to the V853, but UART0 is only on pins PE2/3, using pinmux 6, with no other muxes other than PortF. Signed-off-by: Andre Przywara --- uart0-helloworld-sdboot.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index 105551213..b512e4fdd 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -141,6 +141,7 @@ enum sunxi_gpio_number { #define SUN5I_GPB_UART0 (2) #define SUN6I_GPH_UART0 (2) #define SUN8I_H3_GPA_UART0 (2) +#define SUN8I_R528_GPE_UART0 (6) #define SUN8I_V3S_GPB_UART0 (3) #define SUN8I_V831_GPH_UART0 (5) #define SUN8I_V853_GPH_UART0 (5) @@ -310,6 +311,7 @@ void soc_detection_init(void) #define soc_is_v3s() (soc_id == 0x1681) #define soc_is_v831() (soc_id == 0x1817) #define soc_is_v853() (soc_id == 0x1886) +#define soc_is_r528() (soc_id == 0x1859) /* A10s and A13 share the same ID, so we need a little more effort on those */ @@ -396,7 +398,7 @@ void clock_init_uart(void) { if (soc_is_h6() || soc_is_v831() || soc_is_h616()) clock_init_uart_h6(); - else if (soc_is_r329() || soc_is_v853()) + else if (soc_is_r329() || soc_is_v853() || soc_is_r528()) clock_init_uart_r329(); else clock_init_uart_legacy(); @@ -410,7 +412,7 @@ void clock_init_uart(void) void gpio_init(void) { - if (soc_is_v853()) { + if (soc_is_v853() || soc_is_r528()) { /* GPIO V2 */ pio_bank_size = 0x30; pio_dat_off = 0x10; @@ -478,6 +480,10 @@ void gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(9), SUN8I_V853_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(10), SUN8I_V853_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(10), SUNXI_GPIO_PULL_UP); + } else if (soc_is_r528()) { + sunxi_gpio_set_cfgpin(SUNXI_GPE(2), SUN8I_R528_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPE(3), SUN8I_R528_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); } else { /* Unknown SoC */ while (1) {} @@ -580,7 +586,7 @@ void bases_init(void) } else if (soc_is_r329()) { pio_base = R329_PIO_BASE; uart0_base = R329_UART0_BASE; - } else if (soc_is_v853()) { + } else if (soc_is_v853() || soc_is_r528()) { pio_base = V853_PIO_BASE; uart0_base = R329_UART0_BASE; } else { @@ -629,6 +635,8 @@ int main(void) uart0_puts("Allwinner V831!\n"); else if (soc_is_v853()) uart0_puts("Allwinner V853!\n"); + else if (soc_is_r528()) + uart0_puts("Allwinner R528/T113!\n"); else uart0_puts("unknown Allwinner SoC!\n"); From cbaf572b3d48836c90c3c383cc7dfa618d42de9d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 27 May 2022 23:54:48 +0100 Subject: [PATCH 3/4] fel: add Allwinner V5 SoC support The V5 is (yet another) example of a more recent SoC with A7 cores, so it goes with the H6 memory map and peripherals, but with 32-bit cores. Add basic support, to facilitate development. Signed-off-by: Andre Przywara --- soc_info.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/soc_info.c b/soc_info.c index d0af8ef8f..f37ec5ff0 100644 --- a/soc_info.c +++ b/soc_info.c @@ -421,6 +421,17 @@ soc_info_t soc_info_table[] = { .sid_offset = 0x200, .icache_fix = true, .watchdog = &wd_v853_compat, + },{ + .soc_id = 0x1721, /* Allwinner V5 */ + .name = "V5", + .spl_addr = 0x20000, + .scratch_addr = 0x21000, + .thunk_addr = 0x42200, .thunk_size = 0x200, + .swap_buffers = h6_sram_swap_buffers, + .sram_size = 136 * 1024, + .sid_base = 0x03006000, + .sid_offset = 0x200, + .watchdog = &wd_h6_compat, },{ .swap_buffers = NULL /* End of the table */ } From 91fcdf81fed1cd5d3f824614ca2c15ff324e071d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 28 Jul 2022 22:46:17 +0100 Subject: [PATCH 4/4] uart0-helloworld-sdboot: add V5 support Clock and UART wise close to the H6, but UART0 is only on pins PB9/10, with no other muxes than PortF. Signed-off-by: Andre Przywara --- uart0-helloworld-sdboot.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index b512e4fdd..f2d241de5 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -143,6 +143,7 @@ enum sunxi_gpio_number { #define SUN8I_H3_GPA_UART0 (2) #define SUN8I_R528_GPE_UART0 (6) #define SUN8I_V3S_GPB_UART0 (3) +#define SUN8I_V5_GPB_UART0 (2) #define SUN8I_V831_GPH_UART0 (5) #define SUN8I_V853_GPH_UART0 (5) #define SUN50I_H5_GPA_UART0 (2) @@ -312,6 +313,7 @@ void soc_detection_init(void) #define soc_is_v831() (soc_id == 0x1817) #define soc_is_v853() (soc_id == 0x1886) #define soc_is_r528() (soc_id == 0x1859) +#define soc_is_v5() (soc_id == 0x1721) /* A10s and A13 share the same ID, so we need a little more effort on those */ @@ -396,7 +398,7 @@ void clock_init_uart_r329(void) void clock_init_uart(void) { - if (soc_is_h6() || soc_is_v831() || soc_is_h616()) + if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5()) clock_init_uart_h6(); else if (soc_is_r329() || soc_is_v853() || soc_is_r528()) clock_init_uart_r329(); @@ -484,6 +486,10 @@ void gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPE(2), SUN8I_R528_GPE_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPE(3), SUN8I_R528_GPE_UART0); sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); + } else if (soc_is_v5()) { + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V5_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_V5_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); } else { /* Unknown SoC */ while (1) {} @@ -580,7 +586,7 @@ int get_boot_device(void) void bases_init(void) { - if (soc_is_h6() || soc_is_v831() || soc_is_h616()) { + if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5()) { pio_base = H6_PIO_BASE; uart0_base = H6_UART0_BASE; } else if (soc_is_r329()) { @@ -637,6 +643,8 @@ int main(void) uart0_puts("Allwinner V853!\n"); else if (soc_is_r528()) uart0_puts("Allwinner R528/T113!\n"); + else if (soc_is_v5()) + uart0_puts("Allwinner V5!\n"); else uart0_puts("unknown Allwinner SoC!\n");