|
3 | 3 |
|
4 | 4 | #include "ixgbe_common.h" |
5 | 5 | #include "ixgbe_e610.h" |
| 6 | +#include "ixgbe_x550.h" |
6 | 7 | #include "ixgbe_type.h" |
7 | 8 | #include "ixgbe_x540.h" |
| 9 | +#include "ixgbe_mbx.h" |
8 | 10 | #include "ixgbe_phy.h" |
9 | 11 |
|
10 | 12 | /** |
@@ -2491,3 +2493,166 @@ int ixgbe_validate_eeprom_checksum_e610(struct ixgbe_hw *hw, u16 *checksum_val) |
2491 | 2493 |
|
2492 | 2494 | return err; |
2493 | 2495 | } |
| 2496 | + |
| 2497 | +/** |
| 2498 | + * ixgbe_reset_hw_e610 - Perform hardware reset |
| 2499 | + * @hw: pointer to hardware structure |
| 2500 | + * |
| 2501 | + * Resets the hardware by resetting the transmit and receive units, masks |
| 2502 | + * and clears all interrupts, and performs a reset. |
| 2503 | + * |
| 2504 | + * Return: the exit code of the operation. |
| 2505 | + */ |
| 2506 | +int ixgbe_reset_hw_e610(struct ixgbe_hw *hw) |
| 2507 | +{ |
| 2508 | + u32 swfw_mask = hw->phy.phy_semaphore_mask; |
| 2509 | + u32 ctrl, i; |
| 2510 | + int err; |
| 2511 | + |
| 2512 | + /* Call adapter stop to disable tx/rx and clear interrupts */ |
| 2513 | + err = hw->mac.ops.stop_adapter(hw); |
| 2514 | + if (err) |
| 2515 | + goto reset_hw_out; |
| 2516 | + |
| 2517 | + /* Flush pending Tx transactions. */ |
| 2518 | + ixgbe_clear_tx_pending(hw); |
| 2519 | + |
| 2520 | + hw->phy.ops.init(hw); |
| 2521 | +mac_reset_top: |
| 2522 | + err = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); |
| 2523 | + if (err) |
| 2524 | + return -EBUSY; |
| 2525 | + ctrl = IXGBE_CTRL_RST; |
| 2526 | + ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 2527 | + IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); |
| 2528 | + IXGBE_WRITE_FLUSH(hw); |
| 2529 | + hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
| 2530 | + |
| 2531 | + /* Poll for reset bit to self-clear indicating reset is complete */ |
| 2532 | + for (i = 0; i < 10; i++) { |
| 2533 | + udelay(1); |
| 2534 | + ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 2535 | + if (!(ctrl & IXGBE_CTRL_RST_MASK)) |
| 2536 | + break; |
| 2537 | + } |
| 2538 | + |
| 2539 | + if (ctrl & IXGBE_CTRL_RST_MASK) { |
| 2540 | + struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, |
| 2541 | + hw); |
| 2542 | + |
| 2543 | + err = -EIO; |
| 2544 | + netdev_err(adapter->netdev, "Reset polling failed to complete."); |
| 2545 | + } |
| 2546 | + |
| 2547 | + /* Double resets are required for recovery from certain error |
| 2548 | + * conditions. Between resets, it is necessary to stall to allow time |
| 2549 | + * for any pending HW events to complete. |
| 2550 | + */ |
| 2551 | + msleep(100); |
| 2552 | + if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { |
| 2553 | + hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; |
| 2554 | + goto mac_reset_top; |
| 2555 | + } |
| 2556 | + |
| 2557 | + /* Set the Rx packet buffer size. */ |
| 2558 | + IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), GENMASK(18, 17)); |
| 2559 | + |
| 2560 | + /* Store the permanent mac address */ |
| 2561 | + hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
| 2562 | + |
| 2563 | + /* Maximum number of Receive Address Registers. */ |
| 2564 | +#define IXGBE_MAX_NUM_RAR 128 |
| 2565 | + |
| 2566 | + /* Store MAC address from RAR0, clear receive address registers, and |
| 2567 | + * clear the multicast table. Also reset num_rar_entries to the |
| 2568 | + * maximum number of Receive Address Registers, since we modify this |
| 2569 | + * value when programming the SAN MAC address. |
| 2570 | + */ |
| 2571 | + hw->mac.num_rar_entries = IXGBE_MAX_NUM_RAR; |
| 2572 | + hw->mac.ops.init_rx_addrs(hw); |
| 2573 | + |
| 2574 | + /* Initialize bus function number */ |
| 2575 | + hw->mac.ops.set_lan_id(hw); |
| 2576 | + |
| 2577 | +reset_hw_out: |
| 2578 | + return err; |
| 2579 | +} |
| 2580 | + |
| 2581 | +static const struct ixgbe_mac_operations mac_ops_e610 = { |
| 2582 | + .init_hw = ixgbe_init_hw_generic, |
| 2583 | + .start_hw = ixgbe_start_hw_X540, |
| 2584 | + .clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic, |
| 2585 | + .enable_rx_dma = ixgbe_enable_rx_dma_generic, |
| 2586 | + .get_mac_addr = ixgbe_get_mac_addr_generic, |
| 2587 | + .get_device_caps = ixgbe_get_device_caps_generic, |
| 2588 | + .stop_adapter = ixgbe_stop_adapter_generic, |
| 2589 | + .set_lan_id = ixgbe_set_lan_id_multi_port_pcie, |
| 2590 | + .set_rxpba = ixgbe_set_rxpba_generic, |
| 2591 | + .check_link = ixgbe_check_link_e610, |
| 2592 | + .blink_led_start = ixgbe_blink_led_start_X540, |
| 2593 | + .blink_led_stop = ixgbe_blink_led_stop_X540, |
| 2594 | + .set_rar = ixgbe_set_rar_generic, |
| 2595 | + .clear_rar = ixgbe_clear_rar_generic, |
| 2596 | + .set_vmdq = ixgbe_set_vmdq_generic, |
| 2597 | + .set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic, |
| 2598 | + .clear_vmdq = ixgbe_clear_vmdq_generic, |
| 2599 | + .init_rx_addrs = ixgbe_init_rx_addrs_generic, |
| 2600 | + .update_mc_addr_list = ixgbe_update_mc_addr_list_generic, |
| 2601 | + .enable_mc = ixgbe_enable_mc_generic, |
| 2602 | + .disable_mc = ixgbe_disable_mc_generic, |
| 2603 | + .clear_vfta = ixgbe_clear_vfta_generic, |
| 2604 | + .set_vfta = ixgbe_set_vfta_generic, |
| 2605 | + .fc_enable = ixgbe_fc_enable_generic, |
| 2606 | + .set_fw_drv_ver = ixgbe_set_fw_drv_ver_x550, |
| 2607 | + .init_uta_tables = ixgbe_init_uta_tables_generic, |
| 2608 | + .set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing, |
| 2609 | + .set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing, |
| 2610 | + .set_source_address_pruning = |
| 2611 | + ixgbe_set_source_address_pruning_x550, |
| 2612 | + .set_ethertype_anti_spoofing = |
| 2613 | + ixgbe_set_ethertype_anti_spoofing_x550, |
| 2614 | + .disable_rx_buff = ixgbe_disable_rx_buff_generic, |
| 2615 | + .enable_rx_buff = ixgbe_enable_rx_buff_generic, |
| 2616 | + .enable_rx = ixgbe_enable_rx_generic, |
| 2617 | + .disable_rx = ixgbe_disable_rx_e610, |
| 2618 | + .led_on = ixgbe_led_on_generic, |
| 2619 | + .led_off = ixgbe_led_off_generic, |
| 2620 | + .init_led_link_act = ixgbe_init_led_link_act_generic, |
| 2621 | + .reset_hw = ixgbe_reset_hw_e610, |
| 2622 | + .get_media_type = ixgbe_get_media_type_e610, |
| 2623 | + .setup_link = ixgbe_setup_link_e610, |
| 2624 | + .get_link_capabilities = ixgbe_get_link_capabilities_e610, |
| 2625 | + .get_bus_info = ixgbe_get_bus_info_generic, |
| 2626 | + .acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540, |
| 2627 | + .release_swfw_sync = ixgbe_release_swfw_sync_X540, |
| 2628 | + .init_swfw_sync = ixgbe_init_swfw_sync_X540, |
| 2629 | + .prot_autoc_read = prot_autoc_read_generic, |
| 2630 | + .prot_autoc_write = prot_autoc_write_generic, |
| 2631 | + .setup_fc = ixgbe_setup_fc_e610, |
| 2632 | + .fc_autoneg = ixgbe_fc_autoneg_e610, |
| 2633 | +}; |
| 2634 | + |
| 2635 | +static const struct ixgbe_phy_operations phy_ops_e610 = { |
| 2636 | + .init = ixgbe_init_phy_ops_e610, |
| 2637 | + .identify = ixgbe_identify_phy_e610, |
| 2638 | + .identify_sfp = ixgbe_identify_module_e610, |
| 2639 | + .setup_link_speed = ixgbe_setup_phy_link_speed_generic, |
| 2640 | + .setup_link = ixgbe_setup_phy_link_e610, |
| 2641 | + .enter_lplu = ixgbe_enter_lplu_e610, |
| 2642 | +}; |
| 2643 | + |
| 2644 | +static const struct ixgbe_eeprom_operations eeprom_ops_e610 = { |
| 2645 | + .read = ixgbe_read_ee_aci_e610, |
| 2646 | + .read_buffer = ixgbe_read_ee_aci_buffer_e610, |
| 2647 | + .validate_checksum = ixgbe_validate_eeprom_checksum_e610, |
| 2648 | +}; |
| 2649 | + |
| 2650 | +const struct ixgbe_info ixgbe_e610_info = { |
| 2651 | + .mac = ixgbe_mac_e610, |
| 2652 | + .get_invariants = ixgbe_get_invariants_X540, |
| 2653 | + .mac_ops = &mac_ops_e610, |
| 2654 | + .eeprom_ops = &eeprom_ops_e610, |
| 2655 | + .phy_ops = &phy_ops_e610, |
| 2656 | + .mbx_ops = &mbx_ops_generic, |
| 2657 | + .mvals = ixgbe_mvals_x550em_a, |
| 2658 | +}; |
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