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drm/v3d: fix up register addresses for V3D 7.x
This patch updates a number of register addresses that have been changed in Raspberry Pi 5 (V3D 7.1) and updates the code to use the corresponding registers and addresses based on the actual V3D version. Signed-off-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Maíra Canal <mcanal@igalia.com> Signed-off-by: Maíra Canal <mcanal@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231031073859.25298-3-itoral@igalia.com
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-156
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5 files changed

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‎drivers/gpu/drm/v3d/v3d_debugfs.c‎

Lines changed: 101 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -12,69 +12,83 @@
1212
#include "v3d_drv.h"
1313
#include "v3d_regs.h"
1414

15-
#define REGDEF(reg) { reg, #reg }
15+
#define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg }
1616
struct v3d_reg_def {
17+
u32 min_ver;
18+
u32 max_ver;
1719
u32 reg;
1820
const char *name;
1921
};
2022

2123
static const struct v3d_reg_def v3d_hub_reg_defs[] = {
22-
REGDEF(V3D_HUB_AXICFG),
23-
REGDEF(V3D_HUB_UIFCFG),
24-
REGDEF(V3D_HUB_IDENT0),
25-
REGDEF(V3D_HUB_IDENT1),
26-
REGDEF(V3D_HUB_IDENT2),
27-
REGDEF(V3D_HUB_IDENT3),
28-
REGDEF(V3D_HUB_INT_STS),
29-
REGDEF(V3D_HUB_INT_MSK_STS),
30-
31-
REGDEF(V3D_MMU_CTL),
32-
REGDEF(V3D_MMU_VIO_ADDR),
33-
REGDEF(V3D_MMU_VIO_ID),
34-
REGDEF(V3D_MMU_DEBUG_INFO),
24+
REGDEF(33, 42, V3D_HUB_AXICFG),
25+
REGDEF(33, 71, V3D_HUB_UIFCFG),
26+
REGDEF(33, 71, V3D_HUB_IDENT0),
27+
REGDEF(33, 71, V3D_HUB_IDENT1),
28+
REGDEF(33, 71, V3D_HUB_IDENT2),
29+
REGDEF(33, 71, V3D_HUB_IDENT3),
30+
REGDEF(33, 71, V3D_HUB_INT_STS),
31+
REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
32+
33+
REGDEF(33, 71, V3D_MMU_CTL),
34+
REGDEF(33, 71, V3D_MMU_VIO_ADDR),
35+
REGDEF(33, 71, V3D_MMU_VIO_ID),
36+
REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
37+
38+
REGDEF(71, 71, V3D_GMP_STATUS(71)),
39+
REGDEF(71, 71, V3D_GMP_CFG(71)),
40+
REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
3541
};
3642

3743
static const struct v3d_reg_def v3d_gca_reg_defs[] = {
38-
REGDEF(V3D_GCA_SAFE_SHUTDOWN),
39-
REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
44+
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
45+
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
4046
};
4147

4248
static const struct v3d_reg_def v3d_core_reg_defs[] = {
43-
REGDEF(V3D_CTL_IDENT0),
44-
REGDEF(V3D_CTL_IDENT1),
45-
REGDEF(V3D_CTL_IDENT2),
46-
REGDEF(V3D_CTL_MISCCFG),
47-
REGDEF(V3D_CTL_INT_STS),
48-
REGDEF(V3D_CTL_INT_MSK_STS),
49-
REGDEF(V3D_CLE_CT0CS),
50-
REGDEF(V3D_CLE_CT0CA),
51-
REGDEF(V3D_CLE_CT0EA),
52-
REGDEF(V3D_CLE_CT1CS),
53-
REGDEF(V3D_CLE_CT1CA),
54-
REGDEF(V3D_CLE_CT1EA),
55-
56-
REGDEF(V3D_PTB_BPCA),
57-
REGDEF(V3D_PTB_BPCS),
58-
59-
REGDEF(V3D_GMP_STATUS),
60-
REGDEF(V3D_GMP_CFG),
61-
REGDEF(V3D_GMP_VIO_ADDR),
62-
63-
REGDEF(V3D_ERR_FDBGO),
64-
REGDEF(V3D_ERR_FDBGB),
65-
REGDEF(V3D_ERR_FDBGS),
66-
REGDEF(V3D_ERR_STAT),
49+
REGDEF(33, 71, V3D_CTL_IDENT0),
50+
REGDEF(33, 71, V3D_CTL_IDENT1),
51+
REGDEF(33, 71, V3D_CTL_IDENT2),
52+
REGDEF(33, 71, V3D_CTL_MISCCFG),
53+
REGDEF(33, 71, V3D_CTL_INT_STS),
54+
REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
55+
REGDEF(33, 71, V3D_CLE_CT0CS),
56+
REGDEF(33, 71, V3D_CLE_CT0CA),
57+
REGDEF(33, 71, V3D_CLE_CT0EA),
58+
REGDEF(33, 71, V3D_CLE_CT1CS),
59+
REGDEF(33, 71, V3D_CLE_CT1CA),
60+
REGDEF(33, 71, V3D_CLE_CT1EA),
61+
62+
REGDEF(33, 71, V3D_PTB_BPCA),
63+
REGDEF(33, 71, V3D_PTB_BPCS),
64+
65+
REGDEF(33, 41, V3D_GMP_STATUS(33)),
66+
REGDEF(33, 41, V3D_GMP_CFG(33)),
67+
REGDEF(33, 41, V3D_GMP_VIO_ADDR(33)),
68+
69+
REGDEF(33, 71, V3D_ERR_FDBGO),
70+
REGDEF(33, 71, V3D_ERR_FDBGB),
71+
REGDEF(33, 71, V3D_ERR_FDBGS),
72+
REGDEF(33, 71, V3D_ERR_STAT),
6773
};
6874

6975
static const struct v3d_reg_def v3d_csd_reg_defs[] = {
70-
REGDEF(V3D_CSD_STATUS),
71-
REGDEF(V3D_CSD_CURRENT_CFG0),
72-
REGDEF(V3D_CSD_CURRENT_CFG1),
73-
REGDEF(V3D_CSD_CURRENT_CFG2),
74-
REGDEF(V3D_CSD_CURRENT_CFG3),
75-
REGDEF(V3D_CSD_CURRENT_CFG4),
76-
REGDEF(V3D_CSD_CURRENT_CFG5),
77-
REGDEF(V3D_CSD_CURRENT_CFG6),
76+
REGDEF(41, 71, V3D_CSD_STATUS),
77+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG0(41)),
78+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG1(41)),
79+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG2(41)),
80+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG3(41)),
81+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG4(41)),
82+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG5(41)),
83+
REGDEF(41, 41, V3D_CSD_CURRENT_CFG6(41)),
84+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
85+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
86+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
87+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
88+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
89+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
90+
REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
91+
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
7892
};
7993

8094
static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
@@ -85,38 +99,41 @@ static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
8599
int i, core;
86100

87101
for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
88-
seq_printf(m, "%s (0x%04x): 0x%08x\n",
89-
v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
90-
V3D_READ(v3d_hub_reg_defs[i].reg));
102+
const struct v3d_reg_def *def = &v3d_hub_reg_defs[i];
103+
104+
if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
105+
seq_printf(m, "%s (0x%04x): 0x%08x\n",
106+
def->name, def->reg, V3D_READ(def->reg));
107+
}
91108
}
92109

93-
if (v3d->ver < 41) {
94-
for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
110+
for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
111+
const struct v3d_reg_def *def = &v3d_gca_reg_defs[i];
112+
113+
if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
95114
seq_printf(m, "%s (0x%04x): 0x%08x\n",
96-
v3d_gca_reg_defs[i].name,
97-
v3d_gca_reg_defs[i].reg,
98-
V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
115+
def->name, def->reg, V3D_GCA_READ(def->reg));
99116
}
100117
}
101118

102119
for (core = 0; core < v3d->cores; core++) {
103120
for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
104-
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
105-
core,
106-
v3d_core_reg_defs[i].name,
107-
v3d_core_reg_defs[i].reg,
108-
V3D_CORE_READ(core,
109-
v3d_core_reg_defs[i].reg));
121+
const struct v3d_reg_def *def = &v3d_core_reg_defs[i];
122+
123+
if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
124+
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
125+
core, def->name, def->reg,
126+
V3D_CORE_READ(core, def->reg));
127+
}
110128
}
111129

112-
if (v3d_has_csd(v3d)) {
113-
for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
130+
for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
131+
const struct v3d_reg_def *def = &v3d_csd_reg_defs[i];
132+
133+
if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
114134
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
115-
core,
116-
v3d_csd_reg_defs[i].name,
117-
v3d_csd_reg_defs[i].reg,
118-
V3D_CORE_READ(core,
119-
v3d_csd_reg_defs[i].reg));
135+
core, def->name, def->reg,
136+
V3D_CORE_READ(core, def->reg));
120137
}
121138
}
122139
}
@@ -147,8 +164,10 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
147164
str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
148165
seq_printf(m, "TFU: %s\n",
149166
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
150-
seq_printf(m, "TSY: %s\n",
151-
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
167+
if (v3d->ver <= 42) {
168+
seq_printf(m, "TSY: %s\n",
169+
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
170+
}
152171
seq_printf(m, "MSO: %s\n",
153172
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
154173
seq_printf(m, "L3C: %s (%dkb)\n",
@@ -177,10 +196,14 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
177196
seq_printf(m, " QPUs: %d\n", nslc * qups);
178197
seq_printf(m, " Semaphores: %d\n",
179198
V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
180-
seq_printf(m, " BCG int: %d\n",
181-
(ident2 & V3D_IDENT2_BCG_INT) != 0);
182-
seq_printf(m, " Override TMU: %d\n",
183-
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
199+
if (v3d->ver <= 42) {
200+
seq_printf(m, " BCG int: %d\n",
201+
(ident2 & V3D_IDENT2_BCG_INT) != 0);
202+
}
203+
if (v3d->ver < 40) {
204+
seq_printf(m, " Override TMU: %d\n",
205+
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
206+
}
184207
}
185208

186209
return 0;
@@ -212,14 +235,15 @@ static int v3d_measure_clock(struct seq_file *m, void *unused)
212235
int measure_ms = 1000;
213236

214237
if (v3d->ver >= 40) {
238+
int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
215239
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
216-
V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
240+
V3D_SET_FIELD(cycle_count_reg,
217241
V3D_PCTR_S0));
218242
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
219243
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
220244
} else {
221245
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
222-
V3D_PCTR_CYCLE_COUNT);
246+
V3D_PCTR_CYCLE_COUNT(v3d->ver));
223247
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
224248
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
225249
V3D_V3_PCTR_0_EN_ENABLE |

‎drivers/gpu/drm/v3d/v3d_gem.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@ v3d_init_hw_state(struct v3d_dev *v3d)
4747
static void
4848
v3d_idle_axi(struct v3d_dev *v3d, int core)
4949
{
50-
V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
50+
V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ);
5151

52-
if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
52+
if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) &
5353
(V3D_GMP_STATUS_RD_COUNT_MASK |
5454
V3D_GMP_STATUS_WR_COUNT_MASK |
5555
V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {

‎drivers/gpu/drm/v3d/v3d_irq.c‎

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -19,16 +19,17 @@
1919
#include "v3d_regs.h"
2020
#include "v3d_trace.h"
2121

22-
#define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
23-
V3D_INT_FLDONE | \
24-
V3D_INT_FRDONE | \
25-
V3D_INT_CSDDONE | \
26-
V3D_INT_GMPV))
27-
28-
#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
29-
V3D_HUB_INT_MMU_PTI | \
30-
V3D_HUB_INT_MMU_CAP | \
31-
V3D_HUB_INT_TFUC))
22+
#define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \
23+
V3D_INT_FLDONE | \
24+
V3D_INT_FRDONE | \
25+
V3D_INT_CSDDONE(ver) | \
26+
(ver < 71 ? V3D_INT_GMPV : 0)))
27+
28+
#define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \
29+
V3D_HUB_INT_MMU_PTI | \
30+
V3D_HUB_INT_MMU_CAP | \
31+
V3D_HUB_INT_TFUC | \
32+
(ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0)))
3233

3334
static irqreturn_t
3435
v3d_hub_irq(int irq, void *arg);
@@ -115,7 +116,7 @@ v3d_irq(int irq, void *arg)
115116
status = IRQ_HANDLED;
116117
}
117118

118-
if (intsts & V3D_INT_CSDDONE) {
119+
if (intsts & V3D_INT_CSDDONE(v3d->ver)) {
119120
struct v3d_fence *fence =
120121
to_v3d_fence(v3d->csd_job->base.irq_fence);
121122

@@ -127,7 +128,7 @@ v3d_irq(int irq, void *arg)
127128
/* We shouldn't be triggering these if we have GMP in
128129
* always-allowed mode.
129130
*/
130-
if (intsts & V3D_INT_GMPV)
131+
if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
131132
dev_err(v3d->drm.dev, "GMP violation\n");
132133

133134
/* V3D 4.2 wires the hub and core IRQs together, so if we &
@@ -197,6 +198,11 @@ v3d_hub_irq(int irq, void *arg)
197198
status = IRQ_HANDLED;
198199
}
199200

201+
if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
202+
dev_err(v3d->drm.dev, "GMP Violation\n");
203+
status = IRQ_HANDLED;
204+
}
205+
200206
return status;
201207
}
202208

@@ -211,8 +217,8 @@ v3d_irq_init(struct v3d_dev *v3d)
211217
* for us.
212218
*/
213219
for (core = 0; core < v3d->cores; core++)
214-
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
215-
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
220+
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
221+
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
216222

217223
irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
218224
if (irq1 == -EPROBE_DEFER)
@@ -256,12 +262,12 @@ v3d_irq_enable(struct v3d_dev *v3d)
256262

257263
/* Enable our set of interrupts, masking out any others. */
258264
for (core = 0; core < v3d->cores; core++) {
259-
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
260-
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
265+
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));
266+
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));
261267
}
262268

263-
V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
264-
V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
269+
V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));
270+
V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));
265271
}
266272

267273
void
@@ -276,8 +282,8 @@ v3d_irq_disable(struct v3d_dev *v3d)
276282

277283
/* Clear any pending interrupts we might have left. */
278284
for (core = 0; core < v3d->cores; core++)
279-
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
280-
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
285+
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
286+
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
281287

282288
cancel_work_sync(&v3d->overflow_mem_work);
283289
}

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