Skip to content

Commit 3368b46

Browse files
lightcodelightcode
committed
Add MOV instruction
1 parent 6e414f4 commit 3368b46

10 files changed

Lines changed: 115 additions & 41 deletions

File tree

‎README.md‎

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ HLT : FETCH_PC, FETCH_INST, HALT
3535
STA : FETCH_PC, FETCH_INST, FETCH_PC, LOAD_ADDR, STORE_A
3636
JNZ : FETCH_PC, FETCH_INST, FETCH_PC, JUMP
3737
LDI : FETCH_PC, FETCH_INST, FETCH_PC, LDI
38+
MOV : FETCH_PC, FETCH_INST, MOV_FETCH, MOV_LOAD, MOV_STORE
3839
```
3940

4041
List of all states:
@@ -51,7 +52,10 @@ List of all states:
5152
| `RAM_A` | | | | A | | | | X | | | | |
5253
| `RAM_B` | | | | B | | | | X | | | | |
5354
| `STORE_A` | | | | | A | | | | X | | | |
54-
| `LDI` | | | | op2 | | | | X | | | | |
55+
| `LDI` | | X | | op2 | | | | X | | | | |
56+
| `MOV_FETCH` | | | X | | | | X | | | | | |
57+
| `MOV_LOAD` | | X | | * | * | | * | * | | | | |
58+
| `MOV_STORE` | | | | * | * | | | * | * | | | |
5559

5660
Special cases:
5761

@@ -63,21 +67,21 @@ Graph of the FSM:
6367
```
6468
[0] FETCH_PC
6569
[1] FETCH_INST
66-
|------------+-----------------------|
67-
(HLT) (OUT) (else)
68-
[2] HALT OUT_A FETCH_PC
69-
| | |----------+--------------+--------------------------|
70-
| | (JNZ/JMP/JEZ) (else) (LDI)
71-
[3] NEXT NEXT JUMP LOAD_ADDR LDI
72-
| | |
73-
| |---------|-------------| |
74-
| (STA) (LDA) (ADD/SUB) |
75-
[4] NEXT STORE_A RAM_A RAM_B NEXT
76-
| | |
77-
| | |
78-
[5] NEXT NEXT ALU_OP
79-
|
80-
[6] NEXT
70+
|------------+--------------+--------------------------|
71+
(HLT) (OUT) (MOV) (else)
72+
[2] HALT OUT_A MOV_FETCH FETCH_PC
73+
| | | |----------+--------------+--------------------------|
74+
| | | (JNZ/JMP/JEZ) (else) (LDI)
75+
[3] NEXT NEXT MOV_LOAD JUMP LOAD_ADDR LDI
76+
| | | |
77+
| | |---------|-------------| |
78+
| | (STA) (LDA) (ADD/SUB) |
79+
[4] MOV_STORE NEXT STORE_A RAM_A RAM_B NEXT
80+
| | | |
81+
| | | |
82+
[5] NEXT NEXT NEXT ALU_OP
83+
|
84+
[6] NEXT
8185
```
8286

8387
## Clocks

‎asm/asm.py‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,18 @@
1616
"add": 0b01000000,
1717
"sub": 0b01001000,
1818
"ldi": 0b00010000,
19+
"mov": 0b10000000,
1920
}
2021

2122
reg = {
2223
"A": 0b000,
2324
"B": 0b001,
25+
"C": 0b010,
26+
"D": 0b011,
27+
"E": 0b100,
28+
"F": 0b101,
29+
"G": 0b110,
30+
"M": 0b111,
2431
}
2532

2633
PROGRAM, DATA = 0, 1
@@ -59,6 +66,13 @@
5966
kw[0] = (inst[kw[0]] & 0b11111000) | r
6067
del kw[1]
6168
kw[1] = int(kw[1])
69+
elif current_inst == "mov":
70+
op1 = reg[kw[1]]
71+
op2 = reg[kw[2]]
72+
kw[0] = (inst[kw[0]] & 0b11111000) | op2
73+
kw[0] = (kw[0] & 0b11000111) | (op1 << 3)
74+
del kw[2]
75+
del kw[1]
6276
else:
6377
kw[0] = inst[kw[0]]
6478

‎asm/mov_test.asm‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
.program
2+
3+
start:
4+
5+
ldi B 42
6+
mov M B %k
7+
mov A M %k
8+
out
9+
10+
ldi B 21
11+
mov A B
12+
out
13+
14+
hlt
15+
16+
17+
.data
18+
19+
k = 255

‎gtkwave/config.gtkw‎

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,15 @@
11
[*]
22
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
3-
[*] Thu Aug 31 12:32:00 2017
3+
[*] Fri Sep 1 15:23:54 2017
44
[*]
5-
[dumpfile_size] 52551
5+
[dumpfile] "/home/mgaigniere/Perso/8bit-computer/machine.vcd"
6+
[dumpfile_mtime] "Fri Sep 1 15:17:41 2017"
7+
[dumpfile_size] 9775
8+
[savefile] "/home/mgaigniere/Perso/8bit-computer/gtkwave/config.gtkw"
69
[timestart] 0
710
[size] 1916 1042
8-
[pos] -960 39
9-
*-6.000000 40 170 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
11+
[pos] -961 -1
12+
*-6.000000 201 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
1013
[treeopen] machine_tb.
1114
[treeopen] machine_tb.m_machine.
1215
[treeopen] machine_tb.m_machine.m_cpu.
@@ -30,9 +33,9 @@ machine_tb.m_machine.m_cpu.pc_out[7:0]
3033
@28
3134
machine_tb.m_machine.m_cpu.reset
3235
@2022
33-
^1 /home/mgaigniere/Perso/8bit-computer/gtkwave/states.txt
36+
^1 /home/mgaigniere/Perso/8bit-computer/gtkwave/../../../../../tmp/../home/mgaigniere/Perso/8bit-computer/gtkwave/states.txt
3437
machine_tb.m_machine.m_cpu.state[3:0]
35-
^2 /home/mgaigniere/Perso/8bit-computer/gtkwave/opcode.txt
38+
^2 /home/mgaigniere/Perso/8bit-computer/gtkwave/../../../../../tmp/../home/mgaigniere/Perso/8bit-computer/gtkwave/opcode.txt
3639
machine_tb.m_machine.m_cpu.opcode[7:0]
3740
@1000200
3841
-Control
@@ -45,19 +48,21 @@ machine_tb.m_machine.m_cpu.bus[7:0]
4548
-Bus
4649
@800200
4750
-Registers
51+
@2028
52+
^3 /home/mgaigniere/Perso/8bit-computer/gtkwave/../../../../../tmp/../home/mgaigniere/Perso/8bit-computer/gtkwave/reg-sel.txt
53+
machine_tb.m_machine.m_cpu.sel_in[2:0]
54+
^3 /home/mgaigniere/Perso/8bit-computer/gtkwave/../../../../../tmp/../home/mgaigniere/Perso/8bit-computer/gtkwave/reg-sel.txt
55+
machine_tb.m_machine.m_cpu.sel_out[2:0]
4856
@22
4957
machine_tb.m_machine.m_cpu.m_registers.rega[7:0]
5058
machine_tb.m_machine.m_cpu.m_registers.regb[7:0]
5159
@28
5260
machine_tb.m_machine.m_cpu.rfi
5361
machine_tb.m_machine.m_cpu.rfo
54-
machine_tb.m_machine.m_cpu.sel[2:0]
5562
@1000200
5663
-Registers
5764
@800200
5865
-ALU
59-
@28
60-
machine_tb.m_machine.m_cpu.alu_mode
6166
@22
6267
machine_tb.m_machine.m_cpu.alu_out[7:0]
6368
@1000200

‎gtkwave/reg-sel.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
000 A
2+
001 B
3+
010 C
4+
011 D
5+
100 E
6+
101 F
7+
110 G
8+
111 M

‎gtkwave/states.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,7 @@
99
8 STORE_A
1010
9 LOAD_ADDR
1111
a ALU_OP
12+
b LDI
13+
c MOV_STORE
14+
d MOV_FETCH
15+
e MOV_LOAD

‎rtl/cpu.v‎

Lines changed: 24 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -41,15 +41,17 @@ module cpu(
4141

4242
// General Purpose Registers
4343
// 0 is for accumulator
44-
wire [2:0] sel;
44+
wire [2:0] sel_in;
45+
wire [2:0] sel_out;
4546
wire rfi;
4647
wire rfo;
4748
wire [7:0] rega_out;
4849
wire [7:0] regb_out;
4950
cpu_registers m_registers (
5051
.clk(internal_clk),
5152
.data_in(bus),
52-
.sel(sel),
53+
.sel_in(sel_in),
54+
.sel_out(sel_out),
5355
.enable_write(rfi),
5456
.output_enable(rfo),
5557
.data_out(bus),
@@ -141,31 +143,40 @@ module cpu(
141143
assign operand1 = opcode[5:3];
142144
assign operand2 = opcode[2:0];
143145

146+
wire mov_memory;
147+
assign mov_memory = operand1 == 3'b111 || operand2 == 3'b111;
148+
144149
wire jump_allowed;
145150
assign jump_allowed = opcode == `OP_JMP | (opcode == `OP_JEZ & eq_zero) | (opcode == `OP_JNZ & !eq_zero);
146151

147152
assign c_next = state == `STATE_NEXT | reset;
148153

149154
assign alu_mode = (state == `STATE_ALU_OP) ? operand1 : 'bx;
150155

151-
assign sel = (state == `STATE_ALU_OP | state == `STATE_RAM_A | state == `STATE_OUT_A | state == `STATE_STORE_A) ? 0 :
152-
(state == `STATE_RAM_B) ? 1 :
153-
(state == `STATE_LDI) ? operand2 :
154-
'bx;
155-
assign rfi = state == `STATE_RAM_A | state == `STATE_ALU_OP | state == `STATE_RAM_B | state == `STATE_LDI;
156-
assign rfo = state == `STATE_OUT_A | state == `STATE_STORE_A;
156+
assign sel_in = (state == `STATE_ALU_OP | state == `STATE_RAM_A) ? 0 :
157+
(state == `STATE_RAM_B) ? 1 :
158+
(state == `STATE_LDI) ? operand2 :
159+
(state == `STATE_MOV_STORE) ? operand1 :
160+
'bx;
161+
162+
assign sel_out = (state == `STATE_OUT_A | state == `STATE_STORE_A) ? 0 :
163+
(state == `STATE_MOV_STORE) ? operand2 :
164+
'bx;
165+
166+
assign rfi = state == `STATE_RAM_A | state == `STATE_ALU_OP | state == `STATE_RAM_B | state == `STATE_LDI | (state == `STATE_MOV_STORE && operand1 != 3'b111);
167+
assign rfo = state == `STATE_OUT_A | state == `STATE_STORE_A | (state == `STATE_MOV_STORE && operand2 != 3'b111);
157168

158-
assign c_ci = state == `STATE_FETCH_INST | state == `STATE_JUMP | state == `STATE_LOAD_ADDR;
159-
assign c_co = state == `STATE_FETCH_PC;
169+
assign c_ci = state == `STATE_FETCH_INST | state == `STATE_JUMP | state == `STATE_LOAD_ADDR | state == `STATE_LDI | ((state == `STATE_MOV_LOAD) & mov_memory);
170+
assign c_co = state == `STATE_FETCH_PC | (state == `STATE_MOV_FETCH && mov_memory);
160171
assign c_eo = state == `STATE_ALU_OP;
161172
assign c_halt = state == `STATE_HALT;
162173
assign c_ii = state == `STATE_FETCH_INST;
163174
assign c_j = state == `STATE_JUMP & jump_allowed;
164-
assign c_mi = state == `STATE_FETCH_PC | state == `STATE_LOAD_ADDR;
175+
assign c_mi = state == `STATE_FETCH_PC | state == `STATE_LOAD_ADDR | ((state == `STATE_MOV_FETCH | state == `STATE_MOV_LOAD) & mov_memory);
165176
assign c_oi = state == `STATE_OUT_A;
166177
assign c_ro = state == `STATE_FETCH_INST | (state == `STATE_JUMP & jump_allowed) |
167-
state == `STATE_RAM_A | state == `STATE_RAM_B | state == `STATE_LOAD_ADDR | state == `STATE_LDI;
168-
assign c_ri = state == `STATE_STORE_A;
178+
state == `STATE_RAM_A | state == `STATE_RAM_B | state == `STATE_LOAD_ADDR | state == `STATE_LDI | (state == `STATE_MOV_LOAD & mov_memory) | (state == `STATE_MOV_STORE & operand2 == 3'b111);
179+
assign c_ri = state == `STATE_STORE_A | (state == `STATE_MOV_STORE && operand1 == 3'b111);
169180

170181
wire [3:0] cycle;
171182
cpu_control m_ctrl (

‎rtl/cpu_control.v‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ module cpu_control(
1616
always @ (posedge clk) begin
1717
casez (opcode)
1818
`OP_LDI: opclass = 8'b00_010_000;
19+
`OP_MOV: opclass = 8'b10_000_000;
1920
default: opclass = opcode;
2021
endcase
2122

@@ -24,14 +25,17 @@ module cpu_control(
2425
1: state = `STATE_FETCH_INST;
2526
2: state = (opclass == `OP_HLT) ? `STATE_HALT :
2627
(opclass == `OP_OUT) ? `STATE_OUT_A :
28+
(opclass == 8'b10_000_000) ? `STATE_MOV_FETCH :
2729
`STATE_FETCH_PC;
2830
3: state = (opclass == `OP_HLT || opclass == `OP_OUT) ? `STATE_NEXT :
2931
(opclass == `OP_JMP || opclass == `OP_JEZ || opclass == `OP_JNZ) ? `STATE_JUMP :
3032
(opclass == 8'b00_010_000) ? `STATE_LDI :
33+
(opclass == 8'b10_000_000) ? `STATE_MOV_LOAD :
3134
`STATE_LOAD_ADDR;
3235
4: state = (opclass == `OP_LDA) ? `STATE_RAM_A :
3336
(opclass == `OP_STA) ? `STATE_STORE_A :
3437
(opclass == `OP_ADD || opclass == `OP_SUB) ?`STATE_RAM_B :
38+
(opclass == 8'b10_000_000) ? `STATE_MOV_STORE :
3539
`STATE_NEXT;
3640
5: state = (opclass == `OP_ADD || opclass == `OP_SUB) ? `STATE_ALU_OP :
3741
`STATE_NEXT;

‎rtl/cpu_registers.v‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
module cpu_registers(
22
input wire clk,
33
input wire [7:0] data_in,
4-
input wire [2:0] sel,
4+
input wire [2:0] sel_in,
5+
input wire [2:0] sel_out,
56
input wire enable_write,
67
input wire output_enable,
78
output wire [7:0] data_out,
@@ -13,10 +14,10 @@ module cpu_registers(
1314

1415
always @ (posedge clk) begin
1516
if (enable_write)
16-
registers[sel] = data_in;
17+
registers[sel_in] = data_in;
1718
end
1819

19-
assign data_out = (output_enable) ? registers[sel] : 'bz;
20+
assign data_out = (output_enable) ? registers[sel_out] : 'bz;
2021
assign rega = registers[0];
2122
assign regb = registers[1];
2223

‎rtl/parameters.v‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
`define OP_LDI 8'b00_010_???
1010
`define OP_ADD 8'b01_000_000
1111
`define OP_SUB 8'b01_001_000
12+
`define OP_MOV 8'b10_???_???
1213

1314
`define STATE_NEXT 4'h0
1415
`define STATE_FETCH_PC 4'h1
@@ -22,6 +23,9 @@
2223
`define STATE_LOAD_ADDR 4'h9
2324
`define STATE_ALU_OP 4'ha
2425
`define STATE_LDI 4'hb
26+
`define STATE_MOV_STORE 4'hc
27+
`define STATE_MOV_FETCH 4'hd
28+
`define STATE_MOV_LOAD 4'he
2529

2630
`define ALU_ADD 3'b000
2731
`define ALU_SUB 3'b001

0 commit comments

Comments
 (0)