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Added Fmax test project for Gowin
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‎example_projects/gowin_fmax_test_prj_template_v1/.gitignore

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#------------------------------------------------------------------------------
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# .gitignore for Gowin IDE
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# rename the file to ".gitignore" and place into your Gowin project directory
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#
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# junk files
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*.gprj.user
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impl/gwsynthesis/*.html
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impl/gwsynthesis/*.xml
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impl/gwsynthesis/*.log
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impl/gwsynthesis/*.vg
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# junk directories
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/impl/pnr
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/impl/temp
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‎example_projects/gowin_fmax_test_prj_template_v1/clean_gowin.bat

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@echo off
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rem ------------------------------------------------------------------------------
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rem clean_gowin.bat
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rem published as part of https://github.com/pConst/basic_verilog
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rem Konstantin Pavlov, pavlovconst@gmail.com
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rem ------------------------------------------------------------------------------
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rem Use this file as a boilerplate for your custom clean script
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rem for Gowin IDE projects
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rem preserving .\impl\gwsynthesis\test.prj file
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del /s /f /q .\impl\gwsynthesis\*.html
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del /s /f /q .\impl\gwsynthesis\*.xml
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del /s /f /q .\impl\gwsynthesis\*.log
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del /s /f /q .\impl\gwsynthesis\*.vg
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del /s /f /q .\impl\pnr\*
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rmdir /s /q .\impl\pnr\
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del /s /f /q .\impl\temp\*
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rmdir /s /q .\impl\temp\
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del /s /f /q .*.gprj.user
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pause
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goto :eof
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‎example_projects/gowin_fmax_test_prj_template_v1/impl/gwsynthesis/test.prj

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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW1NR-9C" package="QFN88P" speed="6" partNumber="GW1NR-LV9QN88PC6/I5"/>
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<FileList>
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<File path="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\ip\sys_pll\sys_pll.v" type="verilog"/>
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<File path="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\src\clk_divider.sv" type="verilog"/>
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<File path="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\src\delay.sv" type="verilog"/>
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<File path="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\src\edge_detect.sv" type="verilog"/>
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<File path="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\src\main.sv" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="dsp_balance" value="0"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="J:\basic_verilog\example_projects\gowin_fmax_test_prj_template_v1\impl\gwsynthesis\test.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="1"/>
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<Option type="verilog_language" value="sysv-2017"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>

‎example_projects/gowin_fmax_test_prj_template_v1/impl/project_process_config.json

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{
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"Allow_Duplicate_Modules" : false,
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"Annotated_Properties_for_Analyst" : true,
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"BACKGROUND_PROGRAMMING" : "off",
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"COMPRESS" : false,
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"CRC_CHECK" : true,
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"Clock_Conversion" : true,
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"DONE" : false,
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"DOWNLOAD_SPEED" : "default",
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"Default_Enum_Encoding" : "default",
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"Disable_Insert_Pad" : false,
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"ENCRYPTION_KEY" : false,
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"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
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"FORMAT" : "binary",
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"FSM Compiler" : true,
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"Fanout_Guide" : 10000,
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"Frequency" : "Auto",
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"Generate_Constraint_File_of_Ports" : false,
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"Generate_IBIS_File" : false,
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"Generate_Plain_Text_Timing_Report" : false,
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"Generate_Post_PNR_Simulation_Model_File" : false,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"GwSyn_Loop_Limit" : 2000,
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"HOTBOOT" : false,
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"I2C" : false,
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"I2C_SLAVE_ADDR" : "00",
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"Implicit_Initial_Value_Support" : false,
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"IncludePath" : [
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],
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"Incremental_Compile" : "",
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"MSPI" : false,
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"Multiple_File_Compilation_Unit" : true,
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"Number_of_Critical_Paths" : "",
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"Number_of_Start/End_Points" : "",
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"OUTPUT_BASE_NAME" : "test",
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"POWER_ON_RESET" : false,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,
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"Pipelining" : true,
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"PlaceInRegToIob" : true,
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"PlaceIoRegToIob" : true,
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"PlaceOutRegToIob" : true,
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"Place_Option" : "0",
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : true,
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"Push_Tristates" : true,
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"READY" : false,
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"RECONFIG_N" : false,
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"Ram_RW_Check" : true,
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"Report_Auto-Placed_Io_Information" : false,
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"Resolve_Mixed_Drivers" : false,
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"Resource_Sharing" : true,
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"Retiming" : false,
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"Route_Option" : "0",
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"Run_Timing_Driven" : true,
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"SECURE_MODE" : false,
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"SECURITY_BIT" : true,
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"SPI_FLASH_ADDR" : "00000000",
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"SSPI" : false,
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"Show_All_Warnings" : false,
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"Synthesis On/Off Implemented as Translate On/Off" : false,
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"Synthesize_tool" : "GowinSyn",
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"TopModule" : "",
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"USERCODE" : "default",
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"Unused_Pin" : "As_input_tri_stated_with_pull_up",
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"Update_Compile_Point_Timing_Data" : false,
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"Use_Clock_Period_for_Unconstrainted IO" : false,
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"Use_SCF" : false,
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"VHDL_Standard" : "VHDL_Std_1993",
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"Verilog_Standard" : "Vlg_Std_Sysv2017",
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"WAKE_UP" : "0",
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"Write_Vendor_Constraint_File" : true,
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"dsp_balance" : false,
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"show_all_warnings" : false
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}

‎example_projects/gowin_fmax_test_prj_template_v1/ip/sys_pll/sys_pll.ipc

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[General]
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ipc_version=4
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file=sys_pll
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module=sys_pll
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target_device=gw1nr9c-004
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type=clock_rpll
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version=1.0
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[Config]
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CKLOUTD3=false
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CLKFB_SOURCE=0
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CLKIN_FREQ=27
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CLKOUTD=false
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CLKOUTP=false
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CLKOUT_BYPASS=false
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CLKOUT_DIVIDE_DYN=true
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CLKOUT_FREQ=250
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CLKOUT_TOLERANCE=3
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DYNAMIC=false
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LANG=0
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LOCK_EN=true
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MODE_GENERAL=true
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PLL_PWD=false
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RESET_PLL=false

‎example_projects/gowin_fmax_test_prj_template_v1/ip/sys_pll/sys_pll.mod

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-series GW1NR
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-device GW1NR-9C
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-package QFN88P
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-part_number GW1NR-LV9QN88PC6/I5
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-mod_name sys_pll
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-file_name sys_pll
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-path J:/fpga_tests/fifo_single_clock_reg_v2_test_gw/ip/sys_pll/
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-type PLL
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-rPll true
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-file_type vlg
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-dev_type GW1NR-9C
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-dyn_idiv_sel false
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-idiv_sel 4
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-dyn_fbdiv_sel false
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-fbdiv_sel 37
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-dyn_odiv_sel false
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-odiv_sel 2
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-dyn_da_en false
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-rst_sig false
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-rst_sig_p false
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-fclkin 27
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-clkfb_sel 0
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-en_lock true
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-clkout_bypass false
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-en_clkoutp false
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-clkoutp_bypass false
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-en_clkoutd false
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-clkoutd_bypass false
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-en_clkoutd3 false

‎example_projects/gowin_fmax_test_prj_template_v1/ip/sys_pll/sys_pll.v

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//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: IP file
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//GOWIN Version: V1.9.8.05
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//Part Number: GW1NR-LV9QN88PC6/I5
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//Device: GW1NR-9C
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//Created Time: Sun May 15 09:43:06 2022
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module sys_pll (clkout, lock, clkin);
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output clkout;
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output lock;
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input clkin;
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wire clkoutp_o;
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wire clkoutd_o;
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wire clkoutd3_o;
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wire gw_gnd;
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assign gw_gnd = 1'b0;
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rPLL rpll_inst (
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.CLKOUT(clkout),
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.LOCK(lock),
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.CLKOUTP(clkoutp_o),
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.CLKOUTD(clkoutd_o),
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.CLKOUTD3(clkoutd3_o),
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.RESET(gw_gnd),
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.RESET_P(gw_gnd),
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.CLKIN(clkin),
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.CLKFB(gw_gnd),
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.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
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);
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defparam rpll_inst.FCLKIN = "27";
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defparam rpll_inst.DYN_IDIV_SEL = "false";
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defparam rpll_inst.IDIV_SEL = 3;
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defparam rpll_inst.DYN_FBDIV_SEL = "false";
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defparam rpll_inst.FBDIV_SEL = 36;
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defparam rpll_inst.DYN_ODIV_SEL = "false";
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defparam rpll_inst.ODIV_SEL = 2;
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defparam rpll_inst.PSDA_SEL = "0000";
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defparam rpll_inst.DYN_DA_EN = "false";
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defparam rpll_inst.DUTYDA_SEL = "1000";
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defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
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defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
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defparam rpll_inst.CLKOUT_DLY_STEP = 0;
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defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
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defparam rpll_inst.CLKFB_SEL = "internal";
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defparam rpll_inst.CLKOUT_BYPASS = "false";
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defparam rpll_inst.CLKOUTP_BYPASS = "false";
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defparam rpll_inst.CLKOUTD_BYPASS = "false";
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defparam rpll_inst.DYN_SDIV_SEL = 2;
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defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
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defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
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defparam rpll_inst.DEVICE = "GW1NR-9C";
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endmodule //sys_pll

‎example_projects/gowin_fmax_test_prj_template_v1/ip/sys_pll/sys_pll_tmp.v

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//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: Template file for instantiation
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//GOWIN Version: V1.9.8.05
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//Part Number: GW1NR-LV9QN88PC6/I5
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//Device: GW1NR-9C
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//Created Time: Sun May 15 09:43:06 2022
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//Change the instance name and port connections to the signal names
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//--------Copy here to design--------
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sys_pll your_instance_name(
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.clkout(clkout_o), //output clkout
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.lock(lock_o), //output lock
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.clkin(clkin_i) //input clkin
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);
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//--------Copy end-------------------

‎example_projects/gowin_fmax_test_prj_template_v1/src/clk_divider.sv

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//------------------------------------------------------------------------------
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// clk_divider.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Divides main clock to get derivative slower synchronous clocks
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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clk_divider #(
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.WIDTH( 32 )
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) CD1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module clk_divider #( parameter
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WIDTH = 32
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)(
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input clk,
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input nrst,
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input ena,
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output logic [(WIDTH-1):0] out = '0
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);
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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out[(WIDTH-1):0] <= '0;
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end else if (ena) begin
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out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
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end
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end
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endmodule

‎example_projects/gowin_fmax_test_prj_template_v1/src/clogb2.svh

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//------------------------------------------------------------------------------
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// clogb2.svh
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Calculates counter/address width based on specified vector/RAM depth
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//
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// Function should be instantiated inside a module
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// But you are free to call it from anywhere by its hierarchical name
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//
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// To add clogb2 function to your module:
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// `include "clogb2.svh"
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//
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function integer clogb2;
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input integer depth;
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for( clogb2=0; depth>0; clogb2=clogb2+1 ) begin
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depth = depth >> 1;
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end
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endfunction
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‎example_projects/gowin_fmax_test_prj_template_v1/src/define.svh

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//------------------------------------------------------------------------------
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// Gowin test project template
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// Vivado bugfix ===============================================================
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// This is a workaround for Vivado bug of not providing errors
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// when using undeclared signals in your code
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// See https://forums.xilinx.com/t5/Synthesis/Bug-in-handling-undeclared-signals-in-instance-statement-named/td-p/300127
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//`define VIVADO_MODULE_HEADER `default_nettype none
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//`define VIVADO_MODULE_FOOTER `default_nettype wire
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// Declare these stubs to safely reuse your Vivado modules in non-Xilinx FPGA projects
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`define VIVADO_MODULE_HEADER
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`define VIVADO_MODULE_FOOTER
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// =============================================================================
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`define INC( AVAL ) \
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``AVAL <= ``AVAL + 1'b1;
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`define DEC( AVAL ) \
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``AVAL <= ``AVAL - 1'b1;
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`define SET( AVAL ) \
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``AVAL <= 1'b1;
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`define RESET( AVAL ) \
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``AVAL <= 1'b0;

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