Makefrag

# See LICENSE for license details.

# check RISCV environment variable
ifndef RISCV
$(error Please set environment variable RISCV. Please take a look at README)
endif

MODEL := TestHarness
PROJECT := freechips.rocketchip.system
CXX := g++
CXXFLAGS := -O1
JVM_MEMORY ?= 2G

SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar
SHELL := /bin/bash

FIRRTL_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl.jar
FIRRTL ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver

# Build firrtl.jar and put it where chisel3 can find it.
$(FIRRTL_JAR): $(shell find $(base_dir)/firrtl/src/main/scala -iname "*.scala")
	$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
	touch $(FIRRTL_JAR)
	mkdir -p $(base_dir)/lib
	cp -p $(FIRRTL_JAR) $(base_dir)/lib
# When chisel3 pr 448 is merged, the following extraneous copy may be removed.
	mkdir -p $(base_dir)/chisel3/lib
	cp -p $(FIRRTL_JAR) $(base_dir)/chisel3/lib

# specify source files
src_path := src/main/scala
default_submodules := . hardfloat chisel3
chisel_srcs := $(foreach submodule, $(default_submodules), $(shell find $(base_dir)/$(submodule)/$(src_path) -name "*.scala"))

# translate trace files generated by C++/Verilog simulation
disasm := >
which_disasm := $(shell which spike-dasm 2> /dev/null)
ifneq ($(which_disasm),)
	disasm := | $(which_disasm) $(DISASM_EXTENSION) >
endif

# define time-out for different types of simulation
timeout_cycles       = 10000000
long_timeout_cycles  = 50000000
linux_timeout_cycles = 5000000000

# emacs local variable

# Local Variables:
# mode: makefile
# End: