From 91eeba898d0759733ab7d71b48694334eaedf14c Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 12 Feb 2024 17:51:18 +0200 Subject: [PATCH] soc: xtensa: intel_adsp: restore bootctl with per-core state When exiting PM_STATE_SOFT_OFF, the primary core state is always used to restore bootctl register and the clock and power gating settings. This can lead to problems if non-primary core is powered up and down many times before primary core 0 is powered down the first time. The saved state in core_desc[0].bctl will be null, and as a result- power gating and clock gating is not disabled correctly for non-primary cores. Link: https://github.com/thesofproject/sof/issues/8642 Signed-off-by: Kai Vehmanen --- soc/xtensa/intel_adsp/ace/power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/ace/power.c b/soc/xtensa/intel_adsp/ace/power.c index de925cb5567ba4..9589c9b56567b1 100644 --- a/soc/xtensa/intel_adsp/ace/power.c +++ b/soc/xtensa/intel_adsp/ace/power.c @@ -329,7 +329,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) if (state == PM_STATE_SOFT_OFF) { /* restore clock gating state */ DSPCS.bootctl[cpu].bctl |= - (core_desc[0].bctl & DSPBR_BCTL_WAITIPCG); + (core_desc[cpu].bctl & DSPBR_BCTL_WAITIPCG); #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE if (cpu == 0) {