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Commits on Mar 12, 2023

• HLS template project and scripts update

  pConst

  committed
  454f71e

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• Added ASCII-to-HEX

  pConst

  committed
  8b1b2ef

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• README update

  pConst

  committed
  eb72143

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Commits on Feb 24, 2023

• README update

  pConst

  committed
  3aa5679

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• Added Vitis HLS scripts and example

  pConst

  committed
  d046210

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• Updated Gray functions

  pConst

  committed
  baea106

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Commits on Feb 18, 2023

• CP script update

  pConst

  committed
  0523320

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• Added hex2ascii as a standalone module

  pConst

  committed
  58c10b0

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• Restored simplified Verilog version of delay.sv

  pConst

  committed
  45a1621

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Commits on Feb 5, 2023

• Pattern is being detected in any bit position now

  pConst

  committed
  db681a4

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Commits on Dec 29, 2022

• Added prog script

  pConst

  committed
  fd38354

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• Fixed Questa support in testbench_template

  pConst

  committed
  11ca69c

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Commits on Dec 14, 2022

• Added updater script

  pConst

  committed
  88db449

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• KCPSM dir gitignore

  pConst

  committed
  978bed9

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• Added xilinx board store

  pConst

  committed
  06c2498

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• Updated scripts

  pConst

  committed
  bdfd79b

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Commits on Dec 12, 2022

• Added clean scripts ..

  pConst

  committed
  50300ad

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• Added clean scripts

  pConst

  committed
  ff72cd4

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• Removed obsolete files

  pConst

  committed
  de068b7

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• Updated test prj up to Vivado 2021.2

  pConst

  committed
  c06a419

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Commits on Dec 9, 2022

• More submodules

  pConst

  committed
  72cb6ac

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Commits on Dec 2, 2022

• Added fresh submodule

  pConst

  committed
  b935455

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Commits on Nov 16, 2022

• Add more stats

  pConst

  committed
  f894f09

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• Fix template typo, 'block' paramerer is default

  pConst

  committed
  257c7fd

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Commits on Nov 11, 2022

• Minor fix for read_ahead_buf

  pConst

  committed
  65e4657

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• Added new benchmarks

  pConst

  committed
  a9f7d50

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• Updated Vivado gitignore

  pConst

  committed
  553e74c

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Commits on Nov 10, 2022

• Added XPM sources

  pConst

  committed
  f9cfe39

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• Added swap script

  pConst

  committed
  da92edd

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Commits on Aug 24, 2022

• Added scripts

  pConst

  committed
  2543bcd

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Commits on Jul 29, 2022

• Updated Vivado gitignore

  pConst

  committed
  3d0bb13

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Commits on Jul 12, 2022

• Added Verilog versions of UART components

  pConst

  committed
  b1c07c9

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Commits on Jul 3, 2022

• Updated testbench template

  pConst

  committed
  0d9f67f

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• Update Modelsim gitignore

  pConst

  committed
  5abae53

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Commits on Jun 19, 2022

• Updated tb template with clock gen module

  pConst

  committed
  65c4655

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