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Merge tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc
Pull spi updates from Mark Brown: "No framework work here, only a bunch of driver updates of varying sizes: - Factoring out of the core hardware support from the MXS MMC driver by Marek Vasut to allow the hardware to also be used for SPI. - Lots of error handling cleanups from Guenter Roeck - Removal of the existing Tegra driver which is quite comprehensively broken as detailed in the changelog for the removal. - DT suppport for the PL022 and GPIO drivers. - pinctrl support for OMAP and PL022." Pulling from Mark Brown as Grant Likely is still busy moving. * tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc: (53 commits) spi: remove completely broken Tegra driver spi/imx: set the inactive state of the clock according to the clock polarity spi/pl022: get/put resources on suspend/resume spi/pl022: use more managed resources spi/pl022: Devicetree support w/o platform data spi/s3c64xx: Don't free controller_data on non-dt platforms spi: omap2-mcspi: add pinctrl support spi/pl022: adopt pinctrl support spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function spi/gpio: Fix stub for spi_gpio_probe_dt() spi/mxs: Make the SPI block clock speed configurable via DT spi: spi-sh-hspi: drop frees of devm_ alloc'd data spi/pl022: Fix chipselects pointer computation spi: spi-tle62x0: Use module_spi_driver macro mxs/spi: Rework the mxs_ssp_timeout to be more readable mxs/spi: Decrement the DMA/PIO border mxs/spi: Increment the transfer length only if transfer succeeded mxs/spi: Fix issues when doing long continuous transfer spi: spi-gpio: Add DT bindings spi: spi-gpio: store chipselect information in private structure ...
2 parents 7a9a297 + 536a53a commit 7fe0b14

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* Freescale MX233/MX28 SSP/SPI
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Required properties:
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- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
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- reg: Offset and length of the register set for the device
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- interrupts: Should contain SSP interrupts (error irq first, dma irq second)
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- fsl,ssp-dma-channel: APBX DMA channel for the SSP
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Optional properties:
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- clock-frequency : Input clock frequency to the SPI block in Hz.
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Default is 160000000 Hz.
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Example:
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ssp0: ssp@80010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-spi";
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reg = <0x80010000 0x2000>;
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interrupts = <96 82>;
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fsl,ssp-dma-channel = <0>;
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};

Documentation/devicetree/bindings/spi/spi-bus.txt

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chip selects. Individual drivers can define additional properties to
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support describing the chip select layout.
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Optional property:
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- num-cs : total number of chipselects
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SPI slave nodes must be children of the SPI master node and can
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contain the following properties.
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- reg - (required) chip select address of device.
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SPI-GPIO devicetree bindings
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Required properties:
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- compatible: should be set to "spi-gpio"
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- #address-cells: should be set to <0x1>
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- ranges
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- gpio-sck: GPIO spec for the SCK line to use
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- gpio-miso: GPIO spec for the MISO line to use
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- gpio-mosi: GPIO spec for the MOSI line to use
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- cs-gpios: GPIOs to use for chipselect lines
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- num-chipselects: number of chipselect lines
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Example:
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spi {
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compatible = "spi-gpio";
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#address-cells = <0x1>;
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ranges;
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gpio-sck = <&gpio 95 0>;
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gpio-miso = <&gpio 98 0>;
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gpio-mosi = <&gpio 97 0>;
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cs-gpios = <&gpio 125 0>;
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num-chipselects = <1>;
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/* clients */
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};
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NXP SC18IS602/SCIS603
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Required properties:
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- compatible : Should be one of
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"nxp,sc18is602"
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"nxp,sc18is602b"
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"nxp,sc18is603"
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- reg: I2C bus address
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Optional properties:
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- clock-frequency : external oscillator clock frequency. If not
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specified, the SC18IS602 default frequency (7372000) will be used.
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The clock-frequency property is relevant and needed only if the chip has an
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external oscillator (SC18IS603).
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Example:
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sc18is603@28 {
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compatible = "nxp,sc18is603";
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reg = <0x28>;
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clock-frequency = <14744000>;
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}

Documentation/devicetree/bindings/spi/spi_pl022.txt

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- interrupts : Should contain SPI controller interrupt
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Optional properties:
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- num-cs : total number of chipselects
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- cs-gpios : should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child nodes.
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If unspecified, a single SPI device without a chip select can be used.
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- pl022,autosuspend-delay : delay in ms following transfer completion before
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the runtime power management system suspends the
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device. A setting of 0 indicates no delay and the
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device will be suspended immediately
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- pl022,rt : indicates the controller should run the message pump with realtime
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priority to minimise the transfer latency on the bus (boolean)
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SPI slave nodes must be children of the SPI master node and can
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contain the following properties.
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- pl022,interface : interface type:
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0: SPI
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1: Texas Instruments Synchronous Serial Frame Format
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2: Microwire (Half Duplex)
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- pl022,com-mode : polling, interrupt or dma
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- pl022,rx-level-trig : Rx FIFO watermark level
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- pl022,tx-level-trig : Tx FIFO watermark level
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- pl022,ctrl-len : Microwire interface: Control length
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- pl022,wait-state : Microwire interface: Wait state
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- pl022,duplex : Microwire interface: Full/Half duplex
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Documentation/spi/spi-sc18is602

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Kernel driver spi-sc18is602
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===========================
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Supported chips:
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* NXP SI18IS602/602B/603
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Datasheet: http://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf
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Author:
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Guenter Roeck <linux@roeck-us.net>
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Description
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-----------
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This driver provides connects a NXP SC18IS602/603 I2C-bus to SPI bridge to the
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kernel's SPI core subsystem.
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The driver does not probe for supported chips, since the SI18IS602/603 does not
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support Chip ID registers. You will have to instantiate the devices explicitly.
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Please see Documentation/i2c/instantiating-devices for details.
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Usage Notes
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-----------
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This driver requires the I2C adapter driver to support raw I2C messages. I2C
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adapter drivers which can only handle the SMBus protocol are not supported.
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The maximum SPI message size supported by SC18IS602/603 is 200 bytes. Attempts
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to initiate longer transfers will fail with -EINVAL. EEPROM read operations and
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similar large accesses have to be split into multiple chunks of no more than
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200 bytes per SPI message (128 bytes of data per message is recommended). This
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means that programs such as "cp" or "od", which automatically use large block
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sizes to access a device, can not be used directly to read data from EEPROM.
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Programs such as dd, where the block size can be specified, should be used
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instead.

arch/arm/mach-u300/core.c

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{
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.dev = &uart0_device.dev,
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},
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{
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.dev = &pl022_device.dev,
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},
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{
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.dev = &mmcsd_device.dev,
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},

drivers/clk/mxs/Makefile

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# Makefile for mxs specific clk
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#
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obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o
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obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
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obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
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obj-$(CONFIG_SOC_IMX28) += clk-imx28.o

drivers/clk/mxs/clk-ssp.c

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/*
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* Copyright 2012 DENX Software Engineering, GmbH
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*
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* Pulled from code:
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* Portions copyright (C) 2003 Russell King, PXA MMCI Driver
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* Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
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*
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* Copyright 2008 Embedded Alley Solutions, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/spi/mxs-spi.h>
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void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
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{
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unsigned int ssp_clk, ssp_sck;
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u32 clock_divide, clock_rate;
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u32 val;
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ssp_clk = clk_get_rate(ssp->clk);
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for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
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clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
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clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
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if (clock_rate <= 255)
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break;
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}
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if (clock_divide > 254) {
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dev_err(ssp->dev,
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"%s: cannot set clock to %d\n", __func__, rate);
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return;
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}
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ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
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val = readl(ssp->base + HW_SSP_TIMING(ssp));
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val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
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val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
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val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
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writel(val, ssp->base + HW_SSP_TIMING(ssp));
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ssp->clk_rate = ssp_sck;
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dev_dbg(ssp->dev,
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"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
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__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
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}
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EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);

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