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Commit 9aa3498

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author
Nicolas Ferre
committed
Merge branch 'at91-3.18-trunk/eth' into linux-3.18-at91
2 parents 5957dad + 3eb4263 commit 9aa3498

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2 files changed

+31
-10
lines changed

2 files changed

+31
-10
lines changed

drivers/net/ethernet/cadence/macb.c

Lines changed: 30 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -292,11 +292,14 @@ static void macb_handle_link_change(struct net_device *dev)
292292

293293
spin_unlock_irqrestore(&bp->lock, flags);
294294

295-
if (!IS_ERR(bp->tx_clk))
296-
macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
297-
298295
if (status_change) {
299296
if (phydev->link) {
297+
/* Update the TX clock rate if and only if the link is
298+
* up and there has been a link change.
299+
*/
300+
if (!IS_ERR(bp->tx_clk))
301+
macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
302+
300303
netif_carrier_on(dev);
301304
netdev_info(dev, "link up (%d/%s)\n",
302305
phydev->speed,
@@ -705,6 +708,9 @@ static void gem_rx_refill(struct macb *bp)
705708

706709
/* properly align Ethernet header */
707710
skb_reserve(skb, NET_IP_ALIGN);
711+
} else {
712+
bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
713+
bp->rx_ring[entry].ctrl = 0;
708714
}
709715
}
710716

@@ -976,7 +982,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
976982
struct macb_queue *queue = dev_id;
977983
struct macb *bp = queue->bp;
978984
struct net_device *dev = bp->dev;
979-
u32 status;
985+
u32 status, ctrl;
980986

981987
status = queue_readl(queue, ISR);
982988

@@ -1032,6 +1038,21 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
10321038
* add that if/when we get our hands on a full-blown MII PHY.
10331039
*/
10341040

1041+
/* There is a hardware issue under heavy load where DMA can
1042+
* stop, this causes endless "used buffer descriptor read"
1043+
* interrupts but it can be cleared by re-enabling RX. See
1044+
* the at91 manual, section 41.3.1 or the Zynq manual
1045+
* section 16.7.4 for details.
1046+
*/
1047+
if (status & MACB_BIT(RXUBR)) {
1048+
ctrl = macb_readl(bp, NCR);
1049+
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1050+
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1051+
1052+
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1053+
macb_writel(bp, ISR, MACB_BIT(RXUBR));
1054+
}
1055+
10351056
if (status & MACB_BIT(ISR_ROVR)) {
10361057
/* We missed at least one packet */
10371058
if (macb_is_gem(bp))
@@ -1471,9 +1492,9 @@ static void macb_init_rings(struct macb *bp)
14711492
for (i = 0; i < TX_RING_SIZE; i++) {
14721493
bp->queues[0].tx_ring[i].addr = 0;
14731494
bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1474-
bp->queues[0].tx_head = 0;
1475-
bp->queues[0].tx_tail = 0;
14761495
}
1496+
bp->queues[0].tx_head = 0;
1497+
bp->queues[0].tx_tail = 0;
14771498
bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
14781499

14791500
bp->rx_tail = 0;
@@ -1893,12 +1914,12 @@ struct net_device_stats *macb_get_stats(struct net_device *dev)
18931914
hwstat->rx_oversize_pkts +
18941915
hwstat->rx_jabbers +
18951916
hwstat->rx_undersize_pkts +
1896-
hwstat->sqe_test_errors +
18971917
hwstat->rx_length_mismatch);
18981918
nstat->tx_errors = (hwstat->tx_late_cols +
18991919
hwstat->tx_excessive_cols +
19001920
hwstat->tx_underruns +
1901-
hwstat->tx_carrier_errors);
1921+
hwstat->tx_carrier_errors +
1922+
hwstat->sqe_test_errors);
19021923
nstat->collisions = (hwstat->tx_single_cols +
19031924
hwstat->tx_multiple_cols +
19041925
hwstat->tx_excessive_cols);
@@ -1975,8 +1996,8 @@ static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
19751996
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
19761997
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
19771998

1999+
regs_buff[12] = macb_or_gem_readl(bp, USRIO);
19782000
if (macb_is_gem(bp)) {
1979-
regs_buff[12] = gem_readl(bp, USRIO);
19802001
regs_buff[13] = gem_readl(bp, DMACFG);
19812002
}
19822003
}

drivers/net/ethernet/cadence/macb.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#define _MACB_H
1212

1313
#define MACB_GREGS_NBR 16
14-
#define MACB_GREGS_VERSION 1
14+
#define MACB_GREGS_VERSION 2
1515
#define MACB_MAX_QUEUES 8
1616

1717
/* MACB register offsets */

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