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| 1 | +2024-09-06 Carl Love <cel@linux.ibm.com> |
| 2 | + |
| 3 | + * config/rs6000/rs6000-overload.def (vec_test_lsbb_all_ones, |
| 4 | + vec_test_lsbb_all_zeros): Add built-in instances for vector signed |
| 5 | + char and vector bool char. |
| 6 | + * doc/extend.texi (vec_test_lsbb_all_ones, |
| 7 | + vec_test_lsbb_all_zeros): Add documentation for the |
| 8 | + existing built-ins. |
| 9 | + |
| 10 | +2024-09-06 Tamar Christina <tamar.christina@arm.com> |
| 11 | + |
| 12 | + PR tree-optimization/116628 |
| 13 | + * tree-vect-patterns.cc (vect_recog_cond_store_pattern): Add SSA_NAME |
| 14 | + check on expression. |
| 15 | + |
| 16 | +2024-09-06 Andrew Pinski <quic_apinski@quicinc.com> |
| 17 | + |
| 18 | + PR target/116598 |
| 19 | + * config/aarch64/aarch64.cc (aarch64_lookup_shared_state_flags): Use |
| 20 | + is_attribute_namespace_p and get_attribute_name instead of manually grabbing |
| 21 | + the namespace and name of the attribute. |
| 22 | + |
| 23 | +2024-09-06 Martin Jambor <mjambor@suse.cz> |
| 24 | + |
| 25 | + * passes.def: Move pass_ipa_cdtor_merge before pass_ipa_cp and |
| 26 | + pass_ipa_sra. |
| 27 | + |
| 28 | +2024-09-06 Martin Jambor <mjambor@suse.cz> |
| 29 | + |
| 30 | + PR ipa/115815 |
| 31 | + * cgraph.cc (cgraph_node_cannot_be_local_p_1): Also check |
| 32 | + DECL_STATIC_CONSTRUCTOR and DECL_STATIC_DESTRUCTOR. |
| 33 | + * ipa-visibility.cc (non_local_p): Likewise. |
| 34 | + (cgraph_node::local_p): Delete extraneous line of tabs. |
| 35 | + |
| 36 | +2024-09-06 Richard Biener <rguenther@suse.de> |
| 37 | + |
| 38 | + * tree-vect-slp.cc (vect_analyze_slp): Also handle discovery |
| 39 | + for double reductions. |
| 40 | + |
| 41 | +2024-09-06 Richard Biener <rguenther@suse.de> |
| 42 | + |
| 43 | + * tree-vect-slp.cc (vect_analyze_slp): Perform single-lane |
| 44 | + loop SLP discovery for non-grouped stores. Move check on the root |
| 45 | + for re-doing SLP analysis with a single lane for load/store-lanes |
| 46 | + earlier and make sure we are dealing with a grouped access. |
| 47 | + * tree-vect-stmts.cc (vectorizable_store): Always set |
| 48 | + vec_num for SLP. |
| 49 | + |
| 50 | +2024-09-06 Georg-Johann Lay <avr@gjlay.de> |
| 51 | + |
| 52 | + * config/avr/avr.h: Remove "Atmel" from header comment. |
| 53 | + * config/avr/avr.cc: Same. |
| 54 | + * config/avr/avr.md: Same. |
| 55 | + * config/avr/avr.opt: Same. |
| 56 | + * config/avr/avr-dimode.md: Same. |
| 57 | + * config/avr/avr-fixed.md: Same. |
| 58 | + * config/avr/constraints.md: Same. |
| 59 | + * config/avr/predicates.md: Same. |
| 60 | + * config/avr/avr-log.cc: Same. |
| 61 | + * config/avr/avrlibc.h: Same. |
| 62 | + * config/avr/specs.h: Same. |
| 63 | + * common/config/avr/avr-common.cc: Same. |
| 64 | + * doc/install.texi: Same. |
| 65 | + * config/avr/avr-arch.h: Adjust header comment. |
| 66 | + * config/avr/avr-c.cc: Same. |
| 67 | + * config/avr/avr-mcus.def: Same. |
| 68 | + * config/avr/avr-modes.def: Same. |
| 69 | + * config/avr/avr-passes.cc: Same. |
| 70 | + * config/avr/avr-passes.def: Same. |
| 71 | + * config/avr/avr-protos.h: Same. |
| 72 | + * config/avr/driver-avr.cc: Same. |
| 73 | + * config/avr/elf.h: Same. |
| 74 | + * config/avr/gen-avr-mmcu-specs.cc: Same. |
| 75 | + * config/avr/gen-avr-mmcu-texi.cc: Same. |
| 76 | + |
| 77 | +2024-09-06 Richard Biener <rguenther@suse.de> |
| 78 | + |
| 79 | + PR tree-optimization/116610 |
| 80 | + * tree-vect-loop.cc (vectorizable_induction): Use MINUS_EXPR |
| 81 | + to apply a mask peeling adjustment. |
| 82 | + |
| 83 | +2024-09-06 Richard Biener <rguenther@suse.de> |
| 84 | + |
| 85 | + PR tree-optimization/116609 |
| 86 | + * tree-vect-loop.cc (vectorizable_live_operation_1): Support |
| 87 | + partial vectors for single-lane SLP. |
| 88 | + |
| 89 | +2024-09-06 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> |
| 90 | + |
| 91 | + * config/riscv/riscv.cc (riscv_build_integer): Detect constants |
| 92 | + were the higher half is the lower half inverted. |
| 93 | + |
| 94 | +2024-09-06 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> |
| 95 | + |
| 96 | + * config/riscv/riscv.cc (riscv_build_integer): Detect new case |
| 97 | + of constants that can be improved. |
| 98 | + (riscv_move_integer): Add synthesys for concatening constants |
| 99 | + without Zbkb. |
| 100 | + |
| 101 | +2024-09-06 Pan Li <pan2.li@intel.com> |
| 102 | + |
| 103 | + * match.pd: Add int_fits_type_p check for .SAT_SUB imm operand. |
| 104 | + |
| 105 | +2024-09-06 Pan Li <pan2.li@intel.com> |
| 106 | + |
| 107 | + * match.pd: Add int_fits_type_p check for .SAT_SUB imm operand. |
| 108 | + |
| 109 | +2024-09-06 YunQiang Su <syq@gcc.gnu.org> |
| 110 | + |
| 111 | + * common/config/riscv/riscv-common.cc(riscv_select_multilib_by_abi): |
| 112 | + Fix out of index problem. |
| 113 | + |
| 114 | +2024-09-06 Jason Merrill <jason@redhat.com> |
| 115 | + |
| 116 | + PR c++/46457 |
| 117 | + PR c++/81665 |
| 118 | + * doc/extend.texi: Document flag_enum attribute. |
| 119 | + * doc/invoke.texi: Mention flag_enum in -Wswitch. |
| 120 | + |
| 121 | +2024-09-06 liuhongt <hongtao.liu@intel.com> |
| 122 | + |
| 123 | + PR target/115517 |
| 124 | + * config/i386/sse.md (*avx2_pcmp<mode>3_1): Change predicate |
| 125 | + of operands[1] and operands[2] from nonimmdiate_operand to |
| 126 | + nonimm_or_0_operand. |
| 127 | + |
1 | 128 | 2024-09-05 Jeff Law <jlaw@ventanamicro.com> |
2 | 129 |
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3 | 130 | * config/riscv/riscv.cc (riscv_expand_int_scc): For rv64, use a DI |
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