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Added Example 8 and Intro To Hardware
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‎ipynb-examples/.ipynb_checkpoints/example8-verilog-checkpoint.ipynb‎

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{
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"cells": [
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"# Example 8: Interfacing with Verilog."
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"While there is much more about PyRTL design to discuss, at some point somebody\n",
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"might ask you to do something with your code other than have it print\n",
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"pretty things out to the terminal. We provide **import from and export to\n",
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"Verilog of designs**, export of **waveforms to VCD**, and a set of **transforms\n",
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"that make doing netlist-level transforms and analyis directly in pyrtl easy.**"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 1,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"import pyrtl\n",
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"from pyrtl.analysis import estimate"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 2,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"pyrtl.reset_working_block()"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## Importing From Verilog"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Sometimes it is useful to pull in components written in Verilog to be used\n",
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"as subcomponents of PyRTL designs or to be subject to analysis written over\n",
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"the PyRTL core. One standard format supported by PyRTL is **\"blif\" format:**\n",
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"https://www.ece.cmu.edu/~ee760/760docs/blif.pdf\n",
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"\n",
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"Many tools support outputing hardware designs to this format, including the\n",
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"free open source project \"Yosys\". Blif files can then be imported either\n",
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"as a string or directly from a file name by the function input_from_blif.\n",
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"Here is a simple example of a **1 bit full adder imported and then simulated**\n",
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"from this blif format."
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]
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},
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{
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"cell_type": "code",
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"execution_count": 3,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"full_adder_blif = \"\"\"\n",
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"# Generated by Yosys 0.3.0+ (git sha1 7e758d5, clang 3.4-1ubuntu3 -fPIC -Os)\n",
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".model full_adder\n",
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".inputs x y cin\n",
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".outputs sum cout\n",
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".names $false\n",
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".names $true\n",
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"1\n",
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".names y $not$FA.v:12$3_Y\n",
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"0 1\n",
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".names x $not$FA.v:11$1_Y\n",
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"0 1\n",
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".names cin $not$FA.v:15$6_Y\n",
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"0 1\n",
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".names ind3 ind4 sum\n",
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"1- 1\n",
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"-1 1\n",
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".names $not$FA.v:15$6_Y ind2 ind3\n",
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"11 1\n",
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".names x $not$FA.v:12$3_Y ind1\n",
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"11 1\n",
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".names ind2 $not$FA.v:16$8_Y\n",
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"0 1\n",
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".names cin $not$FA.v:16$8_Y ind4\n",
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"11 1\n",
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".names x y $and$FA.v:19$11_Y\n",
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"11 1\n",
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".names ind0 ind1 ind2\n",
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"1- 1\n",
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"-1 1\n",
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".names cin ind2 $and$FA.v:19$12_Y\n",
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"11 1\n",
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".names $and$FA.v:19$11_Y $and$FA.v:19$12_Y cout\n",
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"1- 1\n",
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"-1 1\n",
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".names $not$FA.v:11$1_Y y ind0\n",
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"11 1\n",
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".end\n",
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"\"\"\""
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]
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},
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{
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"cell_type": "code",
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"execution_count": 4,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"pyrtl.input_from_blif(full_adder_blif)\n",
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"# have to find the actual wire vectors generated from the names in the blif file\n",
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"x, y, cin = [pyrtl.working_block().get_wirevector_by_name(s) for s in ['x', 'y', 'cin']]\n",
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"io_vectors = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 5,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"# we are only going to trace the input and output vectors for clarity\n",
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"sim_trace = pyrtl.SimulationTrace(wires_to_track=io_vectors)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Now simulate the logic with some random inputs"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 6,
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"metadata": {},
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"outputs": [
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{
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"ename": "NameError",
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"evalue": "name 'random' is not defined",
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"output_type": "error",
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"traceback": [
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"\u001b[1;31m---------------------------------------------------------------------------\u001b[0m",
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"\u001b[1;31mNameError\u001b[0m Traceback (most recent call last)",
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"\u001b[1;32m<ipython-input-6-186a99891e24>\u001b[0m in \u001b[0;36m<module>\u001b[1;34m()\u001b[0m\n\u001b[0;32m 3\u001b[0m \u001b[1;31m# here we actually generate random booleans for the inputs\u001b[0m\u001b[1;33m\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0;32m 4\u001b[0m sim.step({\n\u001b[1;32m----> 5\u001b[1;33m \u001b[1;34m'x'\u001b[0m\u001b[1;33m:\u001b[0m \u001b[0mrandom\u001b[0m\u001b[1;33m.\u001b[0m\u001b[0mchoice\u001b[0m\u001b[1;33m(\u001b[0m\u001b[1;33m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1;33m,\u001b[0m \u001b[1;36m1\u001b[0m\u001b[1;33m]\u001b[0m\u001b[1;33m)\u001b[0m\u001b[1;33m,\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0m\u001b[0;32m 6\u001b[0m \u001b[1;34m'y'\u001b[0m\u001b[1;33m:\u001b[0m \u001b[0mrandom\u001b[0m\u001b[1;33m.\u001b[0m\u001b[0mchoice\u001b[0m\u001b[1;33m(\u001b[0m\u001b[1;33m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1;33m,\u001b[0m \u001b[1;36m1\u001b[0m\u001b[1;33m]\u001b[0m\u001b[1;33m)\u001b[0m\u001b[1;33m,\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n\u001b[0;32m 7\u001b[0m \u001b[1;34m'cin'\u001b[0m\u001b[1;33m:\u001b[0m \u001b[0mrandom\u001b[0m\u001b[1;33m.\u001b[0m\u001b[0mchoice\u001b[0m\u001b[1;33m(\u001b[0m\u001b[1;33m[\u001b[0m\u001b[1;36m0\u001b[0m\u001b[1;33m,\u001b[0m \u001b[1;36m1\u001b[0m\u001b[1;33m]\u001b[0m\u001b[1;33m)\u001b[0m\u001b[1;33m\u001b[0m\u001b[0m\n",
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"\u001b[1;31mNameError\u001b[0m: name 'random' is not defined"
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]
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}
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],
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"source": [
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"sim = pyrtl.Simulation(tracer=sim_trace)\n",
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"for i in range(15):\n",
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" # here we actually generate random booleans for the inputs\n",
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" sim.step({\n",
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" 'x': random.choice([0, 1]),\n",
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" 'y': random.choice([0, 1]),\n",
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" 'cin': random.choice([0, 1])\n",
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" })\n",
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"sim_trace.render_trace(symbol_len=5, segment_size=5)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"## Exporting to Verilog\n",
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"\n",
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"However, not only do we want to have a method to import from Verilog, we also\n",
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"want a way to **export it back out to Verilog** as well. To demonstrate PyRTL's\n",
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"ability to export in Verilog, we will create a **sample 3-bit counter**. However\n",
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"unlike the example in example2, we extend it to be **synchronously resetting**."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"pyrtl.reset_working_block()\n",
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"\n",
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"zero = pyrtl.Input(1, 'zero')\n",
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"counter_output = pyrtl.Output(3, 'counter_output')\n",
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"counter = pyrtl.Register(3, 'counter')\n",
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"counter.next <<= pyrtl.mux(zero, counter + 1, 0)\n",
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"counter_output <<= counter"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"The counter **gets 0 in the next cycle if the \"zero\" signal goes high, otherwise just\n",
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"counter + 1.** Note that both \"0\" and \"1\" are bit extended to the proper length and\n",
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"here we are making use of that native add operation.\n",
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"\n",
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"Let's dump this bad boy out\n",
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"to a verilog file and see what is looks like (here we are using StringIO just to\n",
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"print it to a string for demo purposes, most likely you will want to pass a normal\n",
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"open file)."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"print(\"--- PyRTL Representation ---\")\n",
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"print(pyrtl.working_block())\n",
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"print()\n",
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"\n",
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"print(\"--- Verilog for the Counter ---\")\n",
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"with io.StringIO() as vfile:\n",
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" pyrtl.OutputToVerilog(vfile)\n",
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" print(vfile.getvalue())\n",
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"\n",
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"print(\"--- Simulation Results ---\")\n",
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"sim_trace = pyrtl.SimulationTrace([counter_output, zero])\n",
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"sim = pyrtl.Simulation(tracer=sim_trace)\n",
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"for cycle in range(15):\n",
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" sim.step({'zero': random.choice([0, 0, 0, 1])})\n",
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"sim_trace.render_trace()"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"We already did the *\"hard\" work* of generating a test input for this simulation so\n",
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"we might want to reuse that work when we take this design through a verilog toolchain.\n",
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"The class *__OutputVerilogTestbench__ grabs the inputs used in the simulation trace\n",
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"and sets them up in a standard verilog testbench.*"
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"print(\"--- Verilog for the TestBench ---\")\n",
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"with io.StringIO() as tbfile:\n",
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" pyrtl.output_verilog_testbench(dest_file=tbfile, simulation_trace=sim_trace)\n",
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" print(tbfile.getvalue())"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Now let's talk about transformations of the hardware block. \n",
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"Many times when you are\n",
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"doing some hardware-level analysis you might wish to ignore higher level things like\n",
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"multi-bit wirevectors, adds, concatination, etc. and just thing about wires and basic\n",
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"gates. **PyRTL supports \"lowering\" of designs** into this more restricted set of functionality\n",
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"though the function *\"synthesize\".* Once we lower a design to this form we can then **apply\n",
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"basic optimizations** like constant propgation and dead wire elimination as well. By\n",
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"printing it out to verilog we can see exactly how the design changed."
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]
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},
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{
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"cell_type": "code",
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"execution_count": null,
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"metadata": {
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"collapsed": true
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},
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"outputs": [],
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"source": [
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"print(\"--- Optimized Single-bit Verilog for the Counter ---\")\n",
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"pyrtl.synthesize()\n",
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"pyrtl.optimize()\n",
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"\n",
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"with io.StringIO() as vfile:\n",
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" pyrtl.OutputToVerilog(vfile)\n",
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" print(vfile.getvalue())"
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]
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}
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],
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"metadata": {
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"kernelspec": {
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"display_name": "Python 3",
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"language": "python",
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"name": "python3"
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},
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"language_info": {
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"codemirror_mode": {
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},
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"file_extension": ".py",
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"mimetype": "text/x-python",
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"name": "python",
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"nbconvert_exporter": "python",
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"pygments_lexer": "ipython3",
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"version": "3.6.3"
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}
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},
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"nbformat": 4,
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"nbformat_minor": 2
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}

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