Pinned Loading

1. sachin-101/e-Yantra-Robotics-Competition sachin-101/e-Yantra-Robotics-Competition Public

   Tasks of eYRC 2019-20

   Python 1 2

2. spider-tronix/VLSI spider-tronix/VLSI Public archive

   RISC V core implementation using Verilog.

   Verilog 26 3

3. GauravSingh789/Cascaded-SVM-on-FPGA GauravSingh789/Cascaded-SVM-on-FPGA Public

   Implementing a cascaded SVM on FPGA

   Verilog 6 2