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first set of tests pass
1 parent dff1b73 commit 62ae51a

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3 files changed

+54
-13
lines changed

3 files changed

+54
-13
lines changed

lib.rs

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
#![allow(dead_code)]
2-
#![allow(mutable_transmutes)]
31
#![allow(non_camel_case_types)]
42
#![allow(non_snake_case)]
53
#![allow(non_upper_case_globals)]

z80.rs

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@ pub trait z80Ctrl {
1212
fn write_byte(&mut self, addr: u16, value: u8);
1313
fn port_in(&self, addr: u16) -> u8;
1414
fn port_out(&mut self, addr: u16, value: u8);
15+
#[cfg(test)]
16+
fn test_finished(&self) -> bool;
1517
}
1618

1719
#[derive(BitfieldStruct)]
@@ -90,7 +92,7 @@ impl z80 {
9092
c2rust_padding: [0; 6],
9193
}
9294
}
93-
fn init(&mut self) {
95+
pub fn init(&mut self) {
9496
self.pc = 0 as i32 as uint16_t;
9597
self.sp = 0xffff as i32 as uint16_t;
9698
self.ix = 0 as i32 as uint16_t;
@@ -115,6 +117,9 @@ impl z80 {
115117
self.nmi_pending = 0 as i32 as uint8_t;
116118
self.irq_data = 0 as i32 as uint8_t;
117119
}
120+
pub fn step(&mut self) -> u32 {
121+
unsafe { z80_step_s(self) }
122+
}
118123
}
119124

120125
#[derive(Copy, Clone)]
@@ -1066,10 +1071,6 @@ pub unsafe extern "C" fn z80_set_sp(z: *mut z80, mut sp: uint16_t) {
10661071
(*z).sp = sp;
10671072
}
10681073
#[no_mangle]
1069-
pub unsafe extern "C" fn z80_step(z: *mut z80) -> u32 {
1070-
return z80_step_s(z);
1071-
}
1072-
#[no_mangle]
10731074
pub unsafe extern "C" fn z80_step_n(
10741075
z: *mut z80,
10751076
mut cycles: u32,

z80_tests.rs

Lines changed: 48 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
use crate::z80::{z80, z80Ctrl};
22

33
struct Memory {
4-
mem: [u8; 0x10000],
4+
pub mem: [u8; 0x10000],
5+
pub test_finished: bool,
56
}
67

78
impl z80Ctrl for Memory {
@@ -13,17 +14,58 @@ impl z80Ctrl for Memory {
1314
self.mem[addr as usize] = value;
1415
}
1516
fn port_in(&self, addr: u16) -> u8 {
16-
0
17+
0xff
1718
}
1819
fn port_out(&mut self, addr: u16, value: u8) {
20+
self.test_finished = true;
21+
}
22+
fn test_finished(&self) -> bool {
23+
self.test_finished
1924
}
2025
}
2126

22-
#[test]
23-
pub fn main() {
24-
let memory = Box::new(Memory {
27+
fn run_test(rom: &[u8], cyc_expected: u64) {
28+
let mut memory = Box::new(Memory {
2529
mem: [0; 0x10000],
30+
test_finished: false,
2631
});
27-
let cpu = z80::new(memory);
2832

33+
for (i, byte) in rom.iter().enumerate() {
34+
memory.mem[0x100 + i] = *byte;
35+
}
36+
37+
let mut cyc: u64 = 0;
38+
println!("{:#?}", 1);
39+
40+
let mut cpu = z80::new(memory);
41+
cpu.init();
42+
cpu.pc = 0x100;
43+
cpu.ctrl.write_byte(0,0xd3);
44+
cpu.ctrl.write_byte(1,0);
45+
cpu.ctrl.write_byte(5,0xdb);
46+
cpu.ctrl.write_byte(6,0);
47+
cpu.ctrl.write_byte(7,0xc9);
48+
49+
let mut nb_instructions: u64 = 0;
50+
while !cpu.ctrl.test_finished() {
51+
nb_instructions += 1;
52+
cyc = cyc.wrapping_add(cpu.step().into());
53+
}
54+
let diff = cyc_expected.wrapping_sub(cyc);
55+
println!(
56+
"\n*** {} instructions executed on {} cycles (expected={}, diff={})\n\n",
57+
nb_instructions,
58+
cyc,
59+
cyc_expected,
60+
diff,
61+
);
62+
63+
assert_eq!(cyc, cyc_expected);
64+
}
65+
66+
#[test]
67+
pub fn main() {
68+
run_test(include_bytes!("./roms/prelim.com"), 8721);
69+
run_test(include_bytes!("./roms/zexdoc.cim"), 46734978649);
70+
run_test(include_bytes!("roms/zexall.cim"), 46734978649);
2971
}

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