-
Notifications
You must be signed in to change notification settings - Fork 128
/
Copy pathtegra210-emc-core.c
2062 lines (1757 loc) · 56.8 KB
/
tegra210-emc-core.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
#include "tegra210-emc.h"
#include "tegra210-mc.h"
/* CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT 29
#define EMC_CLK_EMC_2X_CLK_SRC_MASK \
(0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
#define EMC_CLK_SOURCE_PLLM_LJ 0x4
#define EMC_CLK_SOURCE_PLLMB_LJ 0x5
#define EMC_CLK_FORCE_CC_TRIGGER BIT(27)
#define EMC_CLK_MC_EMC_SAME_FREQ BIT(16)
#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0
#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK \
(0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL */
#define DLL_CLK_EMC_DLL_CLK_SRC_SHIFT 29
#define DLL_CLK_EMC_DLL_CLK_SRC_MASK \
(0x7 << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT)
#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT 10
#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_MASK \
(0x3 << DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT)
#define PLLM_VCOA 0
#define PLLM_VCOB 1
#define EMC_DLL_SWITCH_OUT 2
#define DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT 0
#define DLL_CLK_EMC_DLL_CLK_DIVISOR_MASK \
(0xff << DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT)
/* MC_EMEM_ARB_MISC0 */
#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ BIT(27)
/* EMC_DATA_BRLSHFT_X */
#define EMC0_EMC_DATA_BRLSHFT_0_INDEX 2
#define EMC1_EMC_DATA_BRLSHFT_0_INDEX 3
#define EMC0_EMC_DATA_BRLSHFT_1_INDEX 4
#define EMC1_EMC_DATA_BRLSHFT_1_INDEX 5
#define TRIM_REG(chan, rank, reg, byte) \
(((EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte ## _MASK & \
next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
rank ## _ ## reg ## _INDEX]) >> \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte ## _SHIFT) \
+ \
(((EMC_DATA_BRLSHFT_ ## rank ## _RANK ## rank ## _BYTE ## \
byte ## _DATA_BRLSHFT_MASK & \
next->trim_perch_regs[EMC ## chan ## \
_EMC_DATA_BRLSHFT_ ## rank ## _INDEX]) >> \
EMC_DATA_BRLSHFT_ ## rank ## _RANK ## rank ## _BYTE ## \
byte ## _DATA_BRLSHFT_SHIFT) * 64))
#define CALC_TEMP(rank, reg, byte1, byte2, n) \
(((new[n] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## \
reg ## _OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte1 ## _SHIFT) & \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte1 ## _MASK) \
| \
((new[n + 1] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ##\
reg ## _OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte2 ## _SHIFT) & \
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ## reg ## \
_OB_DDLL_LONG_DQ_RANK ## rank ## _BYTE ## byte2 ## _MASK))
#define REFRESH_SPEEDUP(value, speedup) \
(((value) & 0xffff0000) | ((value) & 0xffff) * (speedup))
#define LPDDR2_MR4_SRR GENMASK(2, 0)
static const struct tegra210_emc_sequence *tegra210_emc_sequences[] = {
&tegra210_emc_r21021,
};
static const struct tegra210_emc_table_register_offsets
tegra210_emc_table_register_offsets = {
.burst = {
EMC_RC,
EMC_RFC,
EMC_RFCPB,
EMC_REFCTRL2,
EMC_RFC_SLR,
EMC_RAS,
EMC_RP,
EMC_R2W,
EMC_W2R,
EMC_R2P,
EMC_W2P,
EMC_R2R,
EMC_TPPD,
EMC_CCDMW,
EMC_RD_RCD,
EMC_WR_RCD,
EMC_RRD,
EMC_REXT,
EMC_WEXT,
EMC_WDV_CHK,
EMC_WDV,
EMC_WSV,
EMC_WEV,
EMC_WDV_MASK,
EMC_WS_DURATION,
EMC_WE_DURATION,
EMC_QUSE,
EMC_QUSE_WIDTH,
EMC_IBDLY,
EMC_OBDLY,
EMC_EINPUT,
EMC_MRW6,
EMC_EINPUT_DURATION,
EMC_PUTERM_EXTRA,
EMC_PUTERM_WIDTH,
EMC_QRST,
EMC_QSAFE,
EMC_RDV,
EMC_RDV_MASK,
EMC_RDV_EARLY,
EMC_RDV_EARLY_MASK,
EMC_REFRESH,
EMC_BURST_REFRESH_NUM,
EMC_PRE_REFRESH_REQ_CNT,
EMC_PDEX2WR,
EMC_PDEX2RD,
EMC_PCHG2PDEN,
EMC_ACT2PDEN,
EMC_AR2PDEN,
EMC_RW2PDEN,
EMC_CKE2PDEN,
EMC_PDEX2CKE,
EMC_PDEX2MRR,
EMC_TXSR,
EMC_TXSRDLL,
EMC_TCKE,
EMC_TCKESR,
EMC_TPD,
EMC_TFAW,
EMC_TRPAB,
EMC_TCLKSTABLE,
EMC_TCLKSTOP,
EMC_MRW7,
EMC_TREFBW,
EMC_ODT_WRITE,
EMC_FBIO_CFG5,
EMC_FBIO_CFG7,
EMC_CFG_DIG_DLL,
EMC_CFG_DIG_DLL_PERIOD,
EMC_PMACRO_IB_RXRT,
EMC_CFG_PIPE_1,
EMC_CFG_PIPE_2,
EMC_PMACRO_QUSE_DDLL_RANK0_4,
EMC_PMACRO_QUSE_DDLL_RANK0_5,
EMC_PMACRO_QUSE_DDLL_RANK1_4,
EMC_PMACRO_QUSE_DDLL_RANK1_5,
EMC_MRW8,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4,
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5,
EMC_PMACRO_DDLL_LONG_CMD_0,
EMC_PMACRO_DDLL_LONG_CMD_1,
EMC_PMACRO_DDLL_LONG_CMD_2,
EMC_PMACRO_DDLL_LONG_CMD_3,
EMC_PMACRO_DDLL_LONG_CMD_4,
EMC_PMACRO_DDLL_SHORT_CMD_0,
EMC_PMACRO_DDLL_SHORT_CMD_1,
EMC_PMACRO_DDLL_SHORT_CMD_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3,
EMC_TXDSRVTTGEN,
EMC_FDPD_CTRL_DQ,
EMC_FDPD_CTRL_CMD,
EMC_FBIO_SPARE,
EMC_ZCAL_INTERVAL,
EMC_ZCAL_WAIT_CNT,
EMC_MRS_WAIT_CNT,
EMC_MRS_WAIT_CNT2,
EMC_AUTO_CAL_CHANNEL,
EMC_DLL_CFG_0,
EMC_DLL_CFG_1,
EMC_PMACRO_AUTOCAL_CFG_COMMON,
EMC_PMACRO_ZCTRL,
EMC_CFG,
EMC_CFG_PIPE,
EMC_DYN_SELF_REF_CONTROL,
EMC_QPOP,
EMC_DQS_BRLSHFT_0,
EMC_DQS_BRLSHFT_1,
EMC_CMD_BRLSHFT_2,
EMC_CMD_BRLSHFT_3,
EMC_PMACRO_PAD_CFG_CTRL,
EMC_PMACRO_DATA_PAD_RX_CTRL,
EMC_PMACRO_CMD_PAD_RX_CTRL,
EMC_PMACRO_DATA_RX_TERM_MODE,
EMC_PMACRO_CMD_RX_TERM_MODE,
EMC_PMACRO_CMD_PAD_TX_CTRL,
EMC_PMACRO_DATA_PAD_TX_CTRL,
EMC_PMACRO_COMMON_PAD_TX_CTRL,
EMC_PMACRO_VTTGEN_CTRL_0,
EMC_PMACRO_VTTGEN_CTRL_1,
EMC_PMACRO_VTTGEN_CTRL_2,
EMC_PMACRO_BRICK_CTRL_RFU1,
EMC_PMACRO_CMD_BRICK_CTRL_FDPD,
EMC_PMACRO_BRICK_CTRL_RFU2,
EMC_PMACRO_DATA_BRICK_CTRL_FDPD,
EMC_PMACRO_BG_BIAS_CTRL_0,
EMC_CFG_3,
EMC_PMACRO_TX_PWRD_0,
EMC_PMACRO_TX_PWRD_1,
EMC_PMACRO_TX_PWRD_2,
EMC_PMACRO_TX_PWRD_3,
EMC_PMACRO_TX_PWRD_4,
EMC_PMACRO_TX_PWRD_5,
EMC_CONFIG_SAMPLE_DELAY,
EMC_PMACRO_TX_SEL_CLK_SRC_0,
EMC_PMACRO_TX_SEL_CLK_SRC_1,
EMC_PMACRO_TX_SEL_CLK_SRC_2,
EMC_PMACRO_TX_SEL_CLK_SRC_3,
EMC_PMACRO_TX_SEL_CLK_SRC_4,
EMC_PMACRO_TX_SEL_CLK_SRC_5,
EMC_PMACRO_DDLL_BYPASS,
EMC_PMACRO_DDLL_PWRD_0,
EMC_PMACRO_DDLL_PWRD_1,
EMC_PMACRO_DDLL_PWRD_2,
EMC_PMACRO_CMD_CTRL_0,
EMC_PMACRO_CMD_CTRL_1,
EMC_PMACRO_CMD_CTRL_2,
EMC_TR_TIMING_0,
EMC_TR_DVFS,
EMC_TR_CTRL_1,
EMC_TR_RDV,
EMC_TR_QPOP,
EMC_TR_RDV_MASK,
EMC_MRW14,
EMC_TR_QSAFE,
EMC_TR_QRST,
EMC_TRAINING_CTRL,
EMC_TRAINING_SETTLE,
EMC_TRAINING_VREF_SETTLE,
EMC_TRAINING_CA_FINE_CTRL,
EMC_TRAINING_CA_CTRL_MISC,
EMC_TRAINING_CA_CTRL_MISC1,
EMC_TRAINING_CA_VREF_CTRL,
EMC_TRAINING_QUSE_CORS_CTRL,
EMC_TRAINING_QUSE_FINE_CTRL,
EMC_TRAINING_QUSE_CTRL_MISC,
EMC_TRAINING_QUSE_VREF_CTRL,
EMC_TRAINING_READ_FINE_CTRL,
EMC_TRAINING_READ_CTRL_MISC,
EMC_TRAINING_READ_VREF_CTRL,
EMC_TRAINING_WRITE_FINE_CTRL,
EMC_TRAINING_WRITE_CTRL_MISC,
EMC_TRAINING_WRITE_VREF_CTRL,
EMC_TRAINING_MPC,
EMC_MRW15,
},
.trim = {
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2,
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1,
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2,
EMC_PMACRO_IB_VREF_DQS_0,
EMC_PMACRO_IB_VREF_DQS_1,
EMC_PMACRO_IB_VREF_DQ_0,
EMC_PMACRO_IB_VREF_DQ_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2,
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1,
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2,
EMC_PMACRO_QUSE_DDLL_RANK0_0,
EMC_PMACRO_QUSE_DDLL_RANK0_1,
EMC_PMACRO_QUSE_DDLL_RANK0_2,
EMC_PMACRO_QUSE_DDLL_RANK0_3,
EMC_PMACRO_QUSE_DDLL_RANK1_0,
EMC_PMACRO_QUSE_DDLL_RANK1_1,
EMC_PMACRO_QUSE_DDLL_RANK1_2,
EMC_PMACRO_QUSE_DDLL_RANK1_3
},
.burst_mc = {
MC_EMEM_ARB_CFG,
MC_EMEM_ARB_OUTSTANDING_REQ,
MC_EMEM_ARB_REFPB_HP_CTRL,
MC_EMEM_ARB_REFPB_BANK_CTRL,
MC_EMEM_ARB_TIMING_RCD,
MC_EMEM_ARB_TIMING_RP,
MC_EMEM_ARB_TIMING_RC,
MC_EMEM_ARB_TIMING_RAS,
MC_EMEM_ARB_TIMING_FAW,
MC_EMEM_ARB_TIMING_RRD,
MC_EMEM_ARB_TIMING_RAP2PRE,
MC_EMEM_ARB_TIMING_WAP2PRE,
MC_EMEM_ARB_TIMING_R2R,
MC_EMEM_ARB_TIMING_W2W,
MC_EMEM_ARB_TIMING_R2W,
MC_EMEM_ARB_TIMING_CCDMW,
MC_EMEM_ARB_TIMING_W2R,
MC_EMEM_ARB_TIMING_RFCPB,
MC_EMEM_ARB_DA_TURNS,
MC_EMEM_ARB_DA_COVERS,
MC_EMEM_ARB_MISC0,
MC_EMEM_ARB_MISC1,
MC_EMEM_ARB_MISC2,
MC_EMEM_ARB_RING1_THROTTLE,
MC_EMEM_ARB_DHYST_CTRL,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6,
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7,
},
.la_scale = {
MC_MLL_MPCORER_PTSA_RATE,
MC_FTOP_PTSA_RATE,
MC_PTSA_GRANT_DECREMENT,
MC_LATENCY_ALLOWANCE_XUSB_0,
MC_LATENCY_ALLOWANCE_XUSB_1,
MC_LATENCY_ALLOWANCE_TSEC_0,
MC_LATENCY_ALLOWANCE_SDMMCA_0,
MC_LATENCY_ALLOWANCE_SDMMCAA_0,
MC_LATENCY_ALLOWANCE_SDMMC_0,
MC_LATENCY_ALLOWANCE_SDMMCAB_0,
MC_LATENCY_ALLOWANCE_PPCS_0,
MC_LATENCY_ALLOWANCE_PPCS_1,
MC_LATENCY_ALLOWANCE_MPCORE_0,
MC_LATENCY_ALLOWANCE_HC_0,
MC_LATENCY_ALLOWANCE_HC_1,
MC_LATENCY_ALLOWANCE_AVPC_0,
MC_LATENCY_ALLOWANCE_GPU_0,
MC_LATENCY_ALLOWANCE_GPU2_0,
MC_LATENCY_ALLOWANCE_NVENC_0,
MC_LATENCY_ALLOWANCE_NVDEC_0,
MC_LATENCY_ALLOWANCE_VIC_0,
MC_LATENCY_ALLOWANCE_VI2_0,
MC_LATENCY_ALLOWANCE_ISP2_0,
MC_LATENCY_ALLOWANCE_ISP2_1,
},
.burst_per_channel = {
{ .bank = 0, .offset = EMC_MRW10, },
{ .bank = 1, .offset = EMC_MRW10, },
{ .bank = 0, .offset = EMC_MRW11, },
{ .bank = 1, .offset = EMC_MRW11, },
{ .bank = 0, .offset = EMC_MRW12, },
{ .bank = 1, .offset = EMC_MRW12, },
{ .bank = 0, .offset = EMC_MRW13, },
{ .bank = 1, .offset = EMC_MRW13, },
},
.trim_per_channel = {
{ .bank = 0, .offset = EMC_CMD_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_CMD_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_DATA_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_DATA_BRLSHFT_0, },
{ .bank = 0, .offset = EMC_DATA_BRLSHFT_1, },
{ .bank = 1, .offset = EMC_DATA_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_0, },
{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_1, },
{ .bank = 0, .offset = EMC_QUSE_BRLSHFT_2, },
{ .bank = 1, .offset = EMC_QUSE_BRLSHFT_3, },
},
.vref_per_channel = {
{
.bank = 0,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK0,
}, {
.bank = 1,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK0,
}, {
.bank = 0,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK1,
}, {
.bank = 1,
.offset = EMC_TRAINING_OPT_DQS_IB_VREF_RANK1,
},
},
};
static void tegra210_emc_train(struct timer_list *timer)
{
struct tegra210_emc *emc = from_timer(emc, timer, training);
unsigned long flags;
if (!emc->last)
return;
spin_lock_irqsave(&emc->lock, flags);
if (emc->sequence->periodic_compensation)
emc->sequence->periodic_compensation(emc);
spin_unlock_irqrestore(&emc->lock, flags);
mod_timer(&emc->training,
jiffies + msecs_to_jiffies(emc->training_interval));
}
static void tegra210_emc_training_start(struct tegra210_emc *emc)
{
mod_timer(&emc->training,
jiffies + msecs_to_jiffies(emc->training_interval));
}
static void tegra210_emc_training_stop(struct tegra210_emc *emc)
{
del_timer(&emc->training);
}
static unsigned int tegra210_emc_get_temperature(struct tegra210_emc *emc)
{
unsigned long flags;
u32 value, max = 0;
unsigned int i;
spin_lock_irqsave(&emc->lock, flags);
for (i = 0; i < emc->num_devices; i++) {
value = tegra210_emc_mrr_read(emc, i, 4);
if (value & BIT(7))
dev_dbg(emc->dev,
"sensor reading changed for device %u: %08x\n",
i, value);
value = FIELD_GET(LPDDR2_MR4_SRR, value);
if (value > max)
max = value;
}
spin_unlock_irqrestore(&emc->lock, flags);
return max;
}
static void tegra210_emc_poll_refresh(struct timer_list *timer)
{
struct tegra210_emc *emc = from_timer(emc, timer, refresh_timer);
unsigned int temperature;
if (!emc->debugfs.temperature)
temperature = tegra210_emc_get_temperature(emc);
else
temperature = emc->debugfs.temperature;
if (temperature == emc->temperature)
goto reset;
switch (temperature) {
case 0 ... 3:
/* temperature is fine, using regular refresh */
dev_dbg(emc->dev, "switching to nominal refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_NOMINAL);
break;
case 4:
dev_dbg(emc->dev, "switching to 2x refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_2X);
break;
case 5:
dev_dbg(emc->dev, "switching to 4x refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_4X);
break;
case 6 ... 7:
dev_dbg(emc->dev, "switching to throttle refresh...\n");
tegra210_emc_set_refresh(emc, TEGRA210_EMC_REFRESH_THROTTLE);
break;
default:
WARN(1, "invalid DRAM temperature state %u\n", temperature);
return;
}
emc->temperature = temperature;
reset:
if (atomic_read(&emc->refresh_poll) > 0) {
unsigned int interval = emc->refresh_poll_interval;
unsigned int timeout = msecs_to_jiffies(interval);
mod_timer(&emc->refresh_timer, jiffies + timeout);
}
}
static void tegra210_emc_poll_refresh_stop(struct tegra210_emc *emc)
{
atomic_set(&emc->refresh_poll, 0);
del_timer_sync(&emc->refresh_timer);
}
static void tegra210_emc_poll_refresh_start(struct tegra210_emc *emc)
{
atomic_set(&emc->refresh_poll, 1);
mod_timer(&emc->refresh_timer,
jiffies + msecs_to_jiffies(emc->refresh_poll_interval));
}
static int tegra210_emc_cd_max_state(struct thermal_cooling_device *cd,
unsigned long *state)
{
*state = 1;
return 0;
}
static int tegra210_emc_cd_get_state(struct thermal_cooling_device *cd,
unsigned long *state)
{
struct tegra210_emc *emc = cd->devdata;
*state = atomic_read(&emc->refresh_poll);
return 0;
}
static int tegra210_emc_cd_set_state(struct thermal_cooling_device *cd,
unsigned long state)
{
struct tegra210_emc *emc = cd->devdata;
if (state == atomic_read(&emc->refresh_poll))
return 0;
if (state)
tegra210_emc_poll_refresh_start(emc);
else
tegra210_emc_poll_refresh_stop(emc);
return 0;
}
static const struct thermal_cooling_device_ops tegra210_emc_cd_ops = {
.get_max_state = tegra210_emc_cd_max_state,
.get_cur_state = tegra210_emc_cd_get_state,
.set_cur_state = tegra210_emc_cd_set_state,
};
static void tegra210_emc_set_clock(struct tegra210_emc *emc, u32 clksrc)
{
emc->sequence->set_clock(emc, clksrc);
if (emc->next->periodic_training)
tegra210_emc_training_start(emc);
else
tegra210_emc_training_stop(emc);
}
static void tegra210_change_dll_src(struct tegra210_emc *emc,
u32 clksrc)
{
u32 dll_setting = emc->next->dll_clk_src;
u32 emc_clk_src;
u32 emc_clk_div;
emc_clk_src = (clksrc & EMC_CLK_EMC_2X_CLK_SRC_MASK) >>
EMC_CLK_EMC_2X_CLK_SRC_SHIFT;
emc_clk_div = (clksrc & EMC_CLK_EMC_2X_CLK_DIVISOR_MASK) >>
EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT;
dll_setting &= ~(DLL_CLK_EMC_DLL_CLK_SRC_MASK |
DLL_CLK_EMC_DLL_CLK_DIVISOR_MASK);
dll_setting |= emc_clk_src << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT;
dll_setting |= emc_clk_div << DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT;
dll_setting &= ~DLL_CLK_EMC_DLL_DDLL_CLK_SEL_MASK;
if (emc_clk_src == EMC_CLK_SOURCE_PLLMB_LJ)
dll_setting |= (PLLM_VCOB <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
else if (emc_clk_src == EMC_CLK_SOURCE_PLLM_LJ)
dll_setting |= (PLLM_VCOA <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
else
dll_setting |= (EMC_DLL_SWITCH_OUT <<
DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT);
tegra210_clk_emc_dll_update_setting(dll_setting);
if (emc->next->clk_out_enb_x_0_clk_enb_emc_dll)
tegra210_clk_emc_dll_enable(true);
else
tegra210_clk_emc_dll_enable(false);
}
int tegra210_emc_set_refresh(struct tegra210_emc *emc,
enum tegra210_emc_refresh refresh)
{
struct tegra210_emc_timing *timings;
unsigned long flags;
if ((emc->dram_type != DRAM_TYPE_LPDDR2 &&
emc->dram_type != DRAM_TYPE_LPDDR4) ||
!emc->last)
return -ENODEV;
if (refresh > TEGRA210_EMC_REFRESH_THROTTLE)
return -EINVAL;
if (refresh == emc->refresh)
return 0;
spin_lock_irqsave(&emc->lock, flags);
if (refresh == TEGRA210_EMC_REFRESH_THROTTLE && emc->derated)
timings = emc->derated;
else
timings = emc->nominal;
if (timings != emc->timings) {
unsigned int index = emc->last - emc->timings;
u32 clksrc;
clksrc = emc->provider.configs[index].value |
EMC_CLK_FORCE_CC_TRIGGER;
emc->next = &timings[index];
emc->timings = timings;
tegra210_emc_set_clock(emc, clksrc);
} else {
tegra210_emc_adjust_timing(emc, emc->last);
tegra210_emc_timing_update(emc);
if (refresh != TEGRA210_EMC_REFRESH_NOMINAL)
emc_writel(emc, EMC_REF_REF_CMD, EMC_REF);
}
spin_unlock_irqrestore(&emc->lock, flags);
return 0;
}
u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip,
unsigned int address)
{
u32 value, ret = 0;
unsigned int i;
value = (chip & EMC_MRR_DEV_SEL_MASK) << EMC_MRR_DEV_SEL_SHIFT |
(address & EMC_MRR_MA_MASK) << EMC_MRR_MA_SHIFT;
emc_writel(emc, value, EMC_MRR);
for (i = 0; i < emc->num_channels; i++)
WARN(tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_MRR_DIVLD, 1),
"Timed out waiting for MRR %u (ch=%u)\n", address, i);
for (i = 0; i < emc->num_channels; i++) {
value = emc_channel_readl(emc, i, EMC_MRR);
value &= EMC_MRR_DATA_MASK;
ret = (ret << 16) | value;
}
return ret;
}
void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc)
{
int err;
mc_readl(emc->mc, MC_EMEM_ADR_CFG);
emc_readl(emc, EMC_INTSTATUS);
tegra210_clk_emc_update_setting(clksrc);
err = tegra210_emc_wait_for_update(emc, 0, EMC_INTSTATUS,
EMC_INTSTATUS_CLKCHANGE_COMPLETE,
true);
if (err)
dev_warn(emc->dev, "clock change completion error: %d\n", err);
}
struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc,
unsigned long rate)
{
unsigned int i;
for (i = 0; i < emc->num_timings; i++)
if (emc->timings[i].rate * 1000UL == rate)
return &emc->timings[i];
return NULL;
}
int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel,
unsigned int offset, u32 bit_mask, bool state)
{
unsigned int i;
u32 value;
for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; i++) {
value = emc_channel_readl(emc, channel, offset);
if (!!(value & bit_mask) == state)
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set)
{
u32 emc_dbg = emc_readl(emc, EMC_DBG);
if (set)
emc_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG);
else
emc_writel(emc, emc_dbg & ~EMC_DBG_WRITE_MUX_ACTIVE, EMC_DBG);
}
u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next)
{
if (next->emc_emrs & 0x1)
return 0;
return 1;
}
void tegra210_emc_timing_update(struct tegra210_emc *emc)
{
unsigned int i;
int err = 0;
emc_writel(emc, 0x1, EMC_TIMING_CONTROL);
for (i = 0; i < emc->num_channels; i++) {
err |= tegra210_emc_wait_for_update(emc, i, EMC_EMC_STATUS,
EMC_EMC_STATUS_TIMING_UPDATE_STALLED,
false);
}
if (err)
dev_warn(emc->dev, "timing update error: %d\n", err);
}
unsigned long tegra210_emc_actual_osc_clocks(u32 in)
{
if (in < 0x40)
return in * 16;
else if (in < 0x80)
return 2048;
else if (in < 0xc0)
return 4096;
else
return 8192;
}
void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc)
{
u32 mpc_req = 0x4b;
emc_writel(emc, mpc_req, EMC_MPC);
mpc_req = emc_readl(emc, EMC_MPC);
}
u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset)
{
u32 temp = 0, rate = next->rate / 1000;
s32 delta[4], delta_taps[4];
s32 new[] = {
TRIM_REG(0, 0, 0, 0),
TRIM_REG(0, 0, 0, 1),
TRIM_REG(0, 0, 1, 2),
TRIM_REG(0, 0, 1, 3),
TRIM_REG(1, 0, 2, 4),
TRIM_REG(1, 0, 2, 5),
TRIM_REG(1, 0, 3, 6),
TRIM_REG(1, 0, 3, 7),
TRIM_REG(0, 1, 0, 0),
TRIM_REG(0, 1, 0, 1),
TRIM_REG(0, 1, 1, 2),
TRIM_REG(0, 1, 1, 3),
TRIM_REG(1, 1, 2, 4),
TRIM_REG(1, 1, 2, 5),
TRIM_REG(1, 1, 3, 6),
TRIM_REG(1, 1, 3, 7)
};
unsigned i;
switch (offset) {
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2:
case EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3:
case EMC_DATA_BRLSHFT_0:
delta[0] = 128 * (next->current_dram_clktree[C0D0U0] -
next->trained_dram_clktree[C0D0U0]);
delta[1] = 128 * (next->current_dram_clktree[C0D0U1] -
next->trained_dram_clktree[C0D0U1]);
delta[2] = 128 * (next->current_dram_clktree[C1D0U0] -
next->trained_dram_clktree[C1D0U0]);
delta[3] = 128 * (next->current_dram_clktree[C1D0U1] -
next->trained_dram_clktree[C1D0U1]);
delta_taps[0] = (delta[0] * (s32)rate) / 1000000;
delta_taps[1] = (delta[1] * (s32)rate) / 1000000;
delta_taps[2] = (delta[2] * (s32)rate) / 1000000;
delta_taps[3] = (delta[3] * (s32)rate) / 1000000;
for (i = 0; i < 4; i++) {
if ((delta_taps[i] > next->tree_margin) ||
(delta_taps[i] < (-1 * next->tree_margin))) {
new[i * 2] = new[i * 2] + delta_taps[i];
new[i * 2 + 1] = new[i * 2 + 1] +
delta_taps[i];
}
}
if (offset == EMC_DATA_BRLSHFT_0) {
for (i = 0; i < 8; i++)
new[i] = new[i] / 64;
} else {
for (i = 0; i < 8; i++)
new[i] = new[i] % 64;