Rewriting UART modules to SystemVerilog

Author: pConst

UartRx.v

@@ -10,6 +10,10 @@
 //  Features early asynchronous 'busy' reset
 
 
+CAUTION !
+THIS CODE IS OBSOLETE NOW. PLEASE USE "uart_rx.sv" VERSION INSTEAD
+
+
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
 UartRx UR1 (
@@ -85,15 +89,15 @@ always @ (posedge clk) begin
 			end else begin
 				rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1;	// counting and sampling only when 'busy'
 			end
-			
+
 			if (rx_do_sample) begin
 				if (rx_data_9th_bit == 1) begin
 					rx_busy <= 0;		// early asynchronous 'busy' reset
 				end else begin
 					{rx_data[7:0],rx_data_9th_bit} <= {s_rxd, rx_data[7:0]};
 				end	//
 			end // rx_do_sample
-			
+
 		end	// ~rx_busy
 	end // ~nrst
 end

UartTx.v

@@ -11,6 +11,10 @@
 //  If multiple UartTX instances should be inferred - make tx_sample_cntr logic common for all TX instances for effective chip area usage
 
 
+CAUTION !
+THIS CODE IS OBSOLETE NOW. PLEASE USE "uart_tx.sv" VERSION INSTEAD
+
+
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
 UartTx UT1 (
@@ -69,14 +73,14 @@ always @ (posedge clk) begin
 				tx_busy <= 1;
 			end
 		end else begin
-		
+
 			if (tx_do_sample) begin		// next bit
 				{tx_shifter[9:0],txd} <= {tx_shifter[9:0],txd} >> 1;	// txd MUST change only on tx_do_sample although data may be loaded earlier
 				if (~|tx_shifter[9:1]) begin		// early asynchronous 'busy' reset
 					tx_busy <= 0;					// txd still holds data, but shifter is ready to get new info
-				end			
+				end
 			end	// tx_do_sample
-			
+
 		end	// ~tx_busy
 	end // ~nrst
 end

UartTx_UartRx_tb.v

@@ -5,7 +5,12 @@
 
 // INFO --------------------------------------------------------------------------------
 //
-//
+
+
+CAUTION !
+THIS CODE IS OBSOLETE NOW. PLEASE USE "uart_tx.sv", "uart_rx.sv" BLOCKS
+AND THEIR TESTBENCHES INSTEAD
+
 
 `timescale 1ns / 1ps
 
@@ -14,7 +19,7 @@ module SimWrapper();
 reg clk200;
 initial begin
         #0 clk200 = 1;
-        forever 
+        forever
             #2.5 clk200 = ~clk200;
 end
 
@@ -92,7 +97,7 @@ defparam UT1.BAUD = 100_000_000;
 UartRx UR1 (
     .clk(clk200),
     .nrst(nrst),
-	
+
 	.rx_data(),
 	.rx_busy(),
 	.rx_done(),

uart_tx.sv

@@ -0,0 +1,93 @@
+//------------------------------------------------------------------------------
+// uart_tx.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Straightforward yet simple UART transmitter implementation
+//    for FPGA written in Verilog
+//
+//  One stop bit setting is hardcoded
+//  Features continuous data output at BAUD levels up to CLK_HZ / 2
+//  Features early asynchronous 'busy' set and reset to gain time to prepare new data
+//  If multiple UartTX instances should be inferred - make tx_sample_cntr logic
+//    that is common for all TX instances for effective chip area usage
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+uart_tx #(
+  .CLK_HZ( 200_000_000 ),  // in Hertz
+  .BAUD( 9600 )            // max. BAUD is CLK_HZ / 2
+) tx1 (
+  .clk(  ),
+  .nrst( 1'b1 ),
+  //.tx_do_sample(  ),
+  .tx_data(  ),
+  .tx_start(  ),
+  .tx_busy(  ),
+  .txd(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module uart_tx #(
+  CLK_HZ = 200_000_000,
+  BAUD = 9600,
+  bit [15:0] BAUD_DIVISOR = CLK_HZ / BAUD
+)(
+  input clk,
+  input nrst,
+  //input tx_do_sample,
+
+  input [7:0] tx_data,
+  input tx_start,                 // write strobe
+  output logic tx_busy = 1'b0,
+  output logic txd = 1'b1
+);
+
+logic [9:0] tx_shifter = '0;
+logic [15:0] tx_sample_cntr = '0;
+always @ (posedge clk) begin
+  if( (~nrst) || (tx_sample_cntr[15:0] == '0) ) begin
+    tx_sample_cntr[15:0] <= (BAUD_DIVISOR-1'b1);
+  end else begin
+    tx_sample_cntr[15:0] <= tx_sample_cntr[15:0] - 1'b1;
+  end
+end
+
+logic tx_do_sample;
+assign tx_do_sample = (tx_sample_cntr[15:0] == '0);
+
+
+always @ (posedge clk) begin
+  if( ~nrst ) begin
+    tx_busy <= 1'b0;
+    tx_shifter[9:0] <= '0;
+    txd <= 1'b1;
+  end else begin
+    if( ~tx_busy ) begin
+      // asynchronous data load and 'busy' set
+      if( tx_start ) begin
+        tx_shifter[9:0] <= { 1'b1,tx_data[7:0],1'b0 };
+        tx_busy <= 1'b1;
+      end
+    end else begin
+
+      if( tx_do_sample ) begin    // next bit
+        // txd MUST change only on tx_do_sample although data may be loaded earlier
+        { tx_shifter[9:0],txd } <= { tx_shifter[9:0],txd } >> 1;
+        // early asynchronous 'busy' reset
+        if( ~|tx_shifter[9:1] ) begin
+          // txd still holds data, but shifter is ready to get new info
+          tx_busy <= 1'b0;
+        end
+      end // tx_do_sample
+
+    end // ~tx_busy
+  end // ~nrst
+end
+
+endmodule
+