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[CORRECTIVE] Fixed writing values in VHDL generator.
Code.Analysis #767: Commit 09c2814 pushed by teuhom
August 21, 2025 07:09 50m 16s main
August 21, 2025 07:09 50m 16s
[CORRECTIVE] Fixed writing values in VHDL generator.
Generate and deploy docs #18: Commit 09c2814 pushed by teuhom
August 21, 2025 07:09 21s main
August 21, 2025 07:09 21s
[CORRECTIVE] Fixed writing values in VHDL generator.
Check.Build #766: Commit 09c2814 pushed by teuhom
August 21, 2025 07:09 27m 6s main
August 21, 2025 07:09 27m 6s
[CORRECTIVE] Fixed the calculated parameter values.
Generate and deploy docs #17: Commit b5a11f0 pushed by teuhom
August 14, 2025 11:24 17s main
August 14, 2025 11:24 17s
[CORRECTIVE] Fixed the calculated parameter values.
Code.Analysis #766: Commit b5a11f0 pushed by teuhom
August 14, 2025 11:24 49m 57s main
August 14, 2025 11:24 49m 57s
[CORRECTIVE] Fixed the calculated parameter values.
Check.Build #765: Commit b5a11f0 pushed by teuhom
August 14, 2025 11:24 25m 33s main
August 14, 2025 11:24 25m 33s
[ADDITIVE] Add address block dimension and stride visualization
Code.Analysis #764: Commit ac72d73 pushed by hagantsa
July 29, 2025 13:44 37m 25s dim-stride-overhaul
July 29, 2025 13:44 37m 25s
[ADDITIVE] Add address block dimension and stride visualization
Check.Build #763: Commit ac72d73 pushed by hagantsa
July 29, 2025 13:44 27m 37s dim-stride-overhaul
July 29, 2025 13:44 27m 37s
[ADDITIVE] Add register file dimension and stride visualization
Check.Build #762: Commit cabfb9c pushed by hagantsa
July 18, 2025 15:35 26m 28s dim-stride-overhaul
July 18, 2025 15:35 26m 28s
[ADDITIVE] Add register file dimension and stride visualization
Code.Analysis #763: Commit cabfb9c pushed by hagantsa
July 18, 2025 15:35 36m 26s dim-stride-overhaul
July 18, 2025 15:35 36m 26s
[CORRECTIVE] Revert Qt signal updates to restore compatibility
Check.Build #761: Commit e5e4fb6 pushed by hanhisua
July 11, 2025 12:22 27m 17s interconnect-gen
July 11, 2025 12:22 27m 17s
[CORRECTIVE] Revert Qt signal updates to restore compatibility
Code.Analysis #762: Commit e5e4fb6 pushed by hanhisua
July 11, 2025 12:22 51m 58s interconnect-gen
July 11, 2025 12:22 51m 58s
July 11, 2025 11:55 19m 30s
July 11, 2025 11:55 18m 42s
[CORRECTIVE] Fix path of InterconnectGenerator.cpp in PythonAPI.pri
Code.Analysis #760: Commit 0e339fd pushed by hanhisua
July 11, 2025 08:05 50m 40s interconnect-gen
July 11, 2025 08:05 50m 40s
July 11, 2025 08:05 26m 17s
[CORRECTIVE] Update paths in the 'PythonAPI.pri' file
Code.Analysis #759: Commit 4062df6 pushed by hanhisua
July 11, 2025 07:02 22m 17s interconnect-gen
July 11, 2025 07:02 22m 17s
[CORRECTIVE] Update paths in the 'PythonAPI.pri' file
Check.Build #758: Commit 4062df6 pushed by hanhisua
July 11, 2025 07:02 22m 37s interconnect-gen
July 11, 2025 07:02 22m 37s
[CORRECTIVE] Update .pri file by adding missing classes
Check.Build #757: Commit 75903d4 pushed by hanhisua
July 10, 2025 12:31 23m 2s interconnect-gen
July 10, 2025 12:31 23m 2s
[CORRECTIVE] Update .pri file by adding missing classes
Code.Analysis #758: Commit 75903d4 pushed by hanhisua
July 10, 2025 12:31 23m 5s interconnect-gen
July 10, 2025 12:31 23m 5s
July 10, 2025 10:40 23m 8s
July 10, 2025 10:40 22m 56s
July 10, 2025 07:20 14m 45s