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VERSION
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VERSION
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2018-04-05 Revision 1: A quartus learning experience
2018-12-28 Revision 2: Some opcodes executing
2020-09-08 Revision 3: First opcode executing
Simple MOV, SUB, ADD, XOR, OR opcodes working
2020-09-09 Flags implemented in ALU unit.
JMP, JNC, JC, JNZ, JZ, JNS, JS REL8/IMM16 working
2020-09-10 Introduced Gatekeeper unit
Implemented LD [IMM16], DST (Memory reads) and ST SRC, [IMM16] (Memory writes)
2020-09-11 Merged Gatekeeper into Regbank
Implemented LD [C:D], A/B and ST A/B, [C:D]
2021-03-28 Compiles into 290 Logic Elements (*)
2021-04-16 Moved XOR opcode from 13 to 15 since its an exception from IMM8 opcodes.
Compiles into 272 Logic Elements (*)
2021-05-01 Added reset delay in control unit.
Changes to simulate with Altera ModelSim instead of builtin simulator.
Compiles into 286 Logic Elements (*)
2021-05-07 Simplified/optimised controlunit logic
ALU_Cin controlunit logic default value simplification
Included Quartus project files
Compiles into 267 Logic Elements (*)
2021-05-25 Reshuffling ALU instructions to simplify decoding
Added instructions for INC and DEC
Changed ZERO constant to ONE constant
Introduced LD [imm8:reg] instruction but removed [C:D] addressing
Introduced Shift instructions (SHR, SHL, RCR, RCL)
Added c3 machine cycle to distinguish next IROP loading
Compiles into 313 Logic Elements (*)
2021-05-29 Regbank DstSel logic reduction
Compiles into 290 Logic Elements (*)
2021-05-31 Added time analysis constraints file.
2021-06-04 Verified the design on FPGA hardware (Terasic DE10-Nano)
1st test successful @ 12.5MHz running a small test program.
2021-07-** Changes to add an E register, changes so that PC can be set to the value
on the address bus. Changed register names IROP->IR, INPC->PC and IMMA->MR
2021-10-22 vhdcore compiles (optimized @ 40MHz) to 332 Logic Elements (*)
rev3core.bdf compiles (optimized @ 40MHz) to 346 Logic Elements (*)
(*) Including debug outputs and simpleram
on Quartus II 13.0.1 64-bit Web Edition,
device target Cyclone II - EP2C8T144C6
For comparison:
MiSTer MOS6510 implementation compiles to 1,144 Logic Elements
on Quartus II and target device Cyclone II - EP2C8T144C6.
M6800 1,050 Logic Elements 4,100 transistors
MOS6502 1,144 Logic Elements 4,528 transistors