HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

The open-source Zynq 7000 BSP generator for openXC7

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Network Development Kit (NDK) for FPGA cards with example application

An open source USB bootloader for FPGAs

USB Serial on the TinyFPGA BX

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Generate Pinout Datasheet in SVG format, from a CSV source file of pin defintions

Amaranth HDL framework for monitoring, hacking, and developing USB devices

Buildroot config for EBAZ4205

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

A 5$ Xilinx ZYNQ development board.

A huge VHDL library for FPGA development

A translation of the Xilinx XPM library to VHDL for simulation purposes

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

A sniffer for Bluetooth 5 and 4.x LE

A Python package for generating HDL wrappers and top modules for HDL sources

High Speed Data Acquisition over HDMI - FPGA implementation

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A dependency management tool for hardware projects.

FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑

Open Logic FPGA Standard Library

VHDLproc is a VHDL preprocessor