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CPU.java
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CPU.java
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//import javax.swing.event.*;
public class CPU extends Thread
{
/* private static class ThreadLocalWaiting extends ThreadLocal
{
protected boolean pleaseWait=false;
protected synchronized Object InitialValue()
{
return pleaseWait;
}
public synchronized Object get()
{
return pleaseWait;
}
protected synchronized Object set(boolean isWaiting)
{
pleaseWait = isWaiting;
}
}*/
boolean[] visited = new boolean[0x10000];
public static final int BIT7 = 1<<7;
public static final int BIT6 = 1<<6;
public static final int BIT5 = 1<<5;
public static final int BIT4 = 1<<4;
public static final int BIT3 = 1<<3;
public static final int BIT2 = 1<<2;
public static final int BIT1 = 1<<1;
public static final int BIT0 = 1<<0;
private static final int ZERO = BIT7;
private static final int SUBTRACT = BIT6;
private static final int HALF_CARRY = BIT5;
private static final int CARRY = BIT4;
private static final int CYCLES_PER_LINE = 114; // (1048576 Hz/ 9198 Hz)
private int[] ROM;
private int[] ROMbank;
private int[] VRAM;
private int[] RAMbank;
private int[] RAM;
private int[] OAM;
private int[] IO;
private int P1; // $FF00
private int IF; // $FF0F
private int LCDC; // $FF40
private int SCY; // $FF42
private int SCX; // $FF43
private int LY; // $FF44
private int BGP; // $FF47
private int IE; // $FFFF
private int[] HRAM;
private ROM rom;
private GUI gui;
private Sound snd = new Sound();
private int mbc = 0; // ROM only for now
private boolean pleaseWait;
private boolean halt;
//private EventListenerList frameListeners = new EventListenerList();
public CPU(ROM rom, GUI gui)
{
this.rom = rom;
this.gui = gui;
pleaseWait = false; // Not in a waiting state on first run
halt = false;
}
public String toString()
{
return rom.getTitle();
}
public boolean getHalt()
{
return halt;
}
public void setHalt(boolean halt) {
this.halt = halt;
}
public boolean getWaiting()
{
return pleaseWait;
}
public void setWaiting(boolean pleaseWait)
{
this.pleaseWait = pleaseWait;
}
public void joypadInt()
{
IF &= BIT4;
}
private static void genFlagTable(int[][] FLAG_ADD, int[][] FLAG_SUB, int[] FLAG_INC, int[] FLAG_DEC)
{
int result, flag;
for (int a = 0; a <= 256; a++)
for (int b = 0; b <= 255; b++)
{
result = b+a;
flag = 0;
if ((b & 0x0F) + (a & 0x0F) > 0x0F) // carry from bit[3]
flag |= HALF_CARRY;
if (result > 0xFF)
{
result &= 0xFF;
flag |= CARRY;
}
if (result == 0)
flag |= ZERO;
FLAG_ADD[a][b] = flag;
result = b-a;
flag = SUBTRACT;
if ((b & 0x0F) < (a & 0x0F)) // borrow from bit[4]
flag |= HALF_CARRY;
if (result < 0)
{
result &= 0xFF;
flag |= CARRY;
}
if (result == 0)
flag |= ZERO;
FLAG_SUB[a][b] = flag;
}
for (int a = 0; a <= 255; a++)
{
flag = 0;
if ((a & 0x0F) == 0x0F)
flag |= HALF_CARRY;
if (a == 255)
flag |= ZERO;
FLAG_INC[a] = flag;
flag = SUBTRACT;
if ((a & 0x0F) == 0)
flag |= HALF_CARRY;
if (a == 1)
flag |= ZERO;
FLAG_DEC[a] = flag;
}
}
public int readMem(int index)
{
switch (index >> 8)
{
case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0A: case 0x0B: case 0x0C: case 0x0D: case 0x0E: case 0x0F:
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1A: case 0x1B: case 0x1C: case 0x1D: case 0x1E: case 0x1F:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F:
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3A: case 0x3B: case 0x3C: case 0x3D: case 0x3E: case 0x3F:
return ROM[index];
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4A: case 0x4B: case 0x4C: case 0x4D: case 0x4E: case 0x4F:
case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
case 0x58: case 0x59: case 0x5A: case 0x5B: case 0x5C: case 0x5D: case 0x5E: case 0x5F:
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
case 0x68: case 0x69: case 0x6A: case 0x6B: case 0x6C: case 0x6D: case 0x6E: case 0x6F:
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
case 0x78: case 0x79: case 0x7A: case 0x7B: case 0x7C: case 0x7D: case 0x7E: case 0x7F:
return ROMbank[index-0x4000];
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F:
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
case 0x98: case 0x99: case 0x9A: case 0x9B: case 0x9C: case 0x9D: case 0x9E: case 0x9F:
return VRAM[index-0x8000];
case 0xA0: case 0xA1: case 0xA2: case 0xA3: case 0xA4: case 0xA5: case 0xA6: case 0xA7:
case 0xA8: case 0xA9: case 0xAA: case 0xAB: case 0xAC: case 0xAD: case 0xAE: case 0xAF:
case 0xB0: case 0xB1: case 0xB2: case 0xB3: case 0xB4: case 0xB5: case 0xB6: case 0xB7:
case 0xB8: case 0xB9: case 0xBA: case 0xBB: case 0xBC: case 0xBD: case 0xBE: case 0xBF:
return RAMbank[index-0xA000];
case 0xC0: case 0xC1: case 0xC2: case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7:
case 0xC8: case 0xC9: case 0xCA: case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF:
case 0xD0: case 0xD1: case 0xD2: case 0xD3: case 0xD4: case 0xD5: case 0xD6: case 0xD7:
case 0xD8: case 0xD9: case 0xDA: case 0xDB: case 0xDC: case 0xDD: case 0xDE: case 0xDF:
return RAM[index-0xC000];
case 0xFE:
return OAM[index-0xFE00];
case 0xFF:
switch(index)
{
case 0xFF00:
return P1;
case 0xFF0F:
return IF;
case 0xFF40:
return LCDC;
case 0xFF42:
return SCY;
case 0xFF43:
return SCX;
case 0xFF44:
return LY;
case 0xFF47:
return BGP;
case 0xFFFF:
return IE;
default:
return HRAM[index-0xFF00];
}
default: // echo internal RAM if in range [E000, FDFF]
return RAM[index-0xE000];
}
}
public int writeMem(int index, int val)
{
switch(mbc)
{
case 0:
switch (index >> 8)
{
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F:
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
case 0x98: case 0x99: case 0x9A: case 0x9B: case 0x9C: case 0x9D: case 0x9E: case 0x9F:
return (VRAM[index-0x8000] = val);
case 0xA0: case 0xA1: case 0xA2: case 0xA3: case 0xA4: case 0xA5: case 0xA6: case 0xA7:
case 0xA8: case 0xA9: case 0xAA: case 0xAB: case 0xAC: case 0xAD: case 0xAE: case 0xAF:
case 0xB0: case 0xB1: case 0xB2: case 0xB3: case 0xB4: case 0xB5: case 0xB6: case 0xB7:
case 0xB8: case 0xB9: case 0xBA: case 0xBB: case 0xBC: case 0xBD: case 0xBE: case 0xBF:
return (RAMbank[index-0xA000] = val);
case 0xC0: case 0xC1: case 0xC2: case 0xC3: case 0xC4: case 0xC5: case 0xC6: case 0xC7:
case 0xC8: case 0xC9: case 0xCA: case 0xCB: case 0xCC: case 0xCD: case 0xCE: case 0xCF:
case 0xD0: case 0xD1: case 0xD2: case 0xD3: case 0xD4: case 0xD5: case 0xD6: case 0xD7:
case 0xD8: case 0xD9: case 0xDA: case 0xDB: case 0xDC: case 0xDD: case 0xDE: case 0xDF:
return (RAM[index-0xC000] = val);
case 0xE0: case 0xE1: case 0xE2: case 0xE3: case 0xE4: case 0xE5: case 0xE6: case 0xE7:
case 0xE8: case 0xE9: case 0xEA: case 0xEB: case 0xEC: case 0xED: case 0xEE: case 0xEF:
case 0xF0: case 0xF1: case 0xF2: case 0xF3: case 0xF4: case 0xF5: case 0xF6: case 0xF7:
case 0xF8: case 0xF9: case 0xFA: case 0xFB: case 0xFC: case 0xFD:
return (RAM[index-0xE000] = val); // echo internal RAM if in range [E000, FDFF]
case 0xFE:
return (OAM[index-0xFE00] = val);
case 0xFF:
switch(index)
{
// Handle IO ports
case 0xFF00: //Joypad
return (P1 = (val & 0xF0));
case 0xFF10: //Channel 1, Sweep
snd.channel1.setSweep(val);
break;
case 0xFF11: //Channel 1, Length/Wave Duty
snd.channel1.setDutyCycle(val);
snd.channel1.setLength(val);
break;
case 0xFF12: //Channel 1, Volume Envelope
snd.channel1.setEnvelope(val);
break;
case 0xFF13: //Channel 1, Low 8 Frequency
snd.channel1.setFrequencyLo(val);
index=0xFF14;
break;
case 0xFF14: //Channel 1, High 3 Frequency
snd.channel1.setFrequencyHi(val);
index=0xFF13;
break;
case 0xFF0F:
return (IF = val);
case 0xFF40:
return (LCDC = val);
case 0xFF42:
return (SCY = val);
case 0xFF43:
return (SCX = val);
case 0xFF44:
return (LY = val);
case 0xFF47:
return (BGP = val);
case 0xFFFF:
return (IE = val);
default:
{
//System.out.printf("Writing %d to %4X\n", val, index);
return (HRAM[index-0xFF00] = val);
}
}
default:
return val; // cannot write to ROM
}
case 1:
switch (index >> 8)
{
//...
}
break;
case 2:
switch (index >> 8)
{
//...
}
break;
case 3:
switch (index >> 8)
{
//...
}
break;
case 5:
switch (index >> 8)
{
//...
}
break;
default: throw new AssertionError("Invalid MBC type");
}
throw new AssertionError("writeMem() did not return a value");
}
public void run()
{
int AREG=0x01;
int FREG=0xB0;
int BREG=0x00;
int CREG=0x13;
int DREG=0x00;
int EREG=0xD8;
int HREG=0x01;
int LREG=0x4D;
int SP=0xFFFE;
int PC=0x0100;
boolean IME = true;
ROM = rom.getDefaultROM();
ROMbank = rom.getROM(1);
VRAM = new int[0x2000];
RAMbank = rom.getRAM(0); // can be null
if (RAMbank == null)
RAMbank = new int[0x2000];
RAM = new int[0x2000];
OAM = new int[0x0100];
//IO = new int[0x0080];
HRAM = new int[0x0100];
int[][] FLAG_ADD = new int[257][256]; // max 255 + 1 (carry) = 256;
int[][] FLAG_SUB = new int[257][256];
int[] FLAG_INC = new int[256];
int[] FLAG_DEC = new int[256];
int val;
int memval;
int index;
int frameCount = 0;
int numCycles = 0;
int scanline = 0;
int nextHBlank = CYCLES_PER_LINE;
int nextVBlank = CYCLES_PER_LINE*144;
int[] colorBG = new int[4];
int[] colorSP0 = new int[4];
int[] colorSP1 = new int[4];
int[] screen = new int[GUI.screenWidth * GUI.screenHeight];
final int[] color = {0xFFFFFFFF, 0xFFC0C0C0, 0xFF404040, 0xFF000000}; // WHITE, LIGHT_GRAY, DARK_GRAY, BLACK
genFlagTable(FLAG_ADD, FLAG_SUB, FLAG_INC, FLAG_DEC);
/*for (int q = 0; q < 256; q++)
{
System.out.println(q + ": " + Integer.toBinaryString(FLAG_DEC[q]));
}*/
long startT = System.nanoTime();
for(;;) // loop until thread stops
{
// Check if should perform actions
synchronized (this) {
while (pleaseWait) {
try {
wait();
} catch (Exception e) {/*maybe print something here*/}
}
if(halt){
return;
}
}
while (scanline <= 153) // from 144 to 153 is v-blank period
{
if (!visited[PC])
{
System.out.printf("Instruction %02X at %04X\n", readMem(PC), PC);
System.out.printf("A: %02X, B: %02X, C: %02X, D: %02X, E: %02X, F: %02X, H: %02X, L: %02X, SP: %04X\n", AREG, BREG, CREG, DREG, EREG, FREG, HREG, LREG, SP);
visited[PC] = true;
}
//if (PC > 0x219)
/*{
if(readMem(PC)!=0xCB)
System.out.format("Operation 0x%02X at 0x%04X\n",readMem(PC),PC);
else
System.out.format("Operation 0x%02X 0x%02X at 0x%04X\n",readMem(PC),readMem(PC+1),PC);
}*/
//if (numCycles > 2000) return;
switch(readMem(PC++))
{
case 0x00: //NOP
numCycles++;
break;
case 0x01: //LD BC,nn
numCycles+=3;
CREG = readMem(PC++);
BREG = readMem(PC++);
break;
case 0x02: //LD (BC),A
numCycles+=2;
writeMem((BREG << 8) | CREG, AREG);
break;
case 0x03: // INC BC
numCycles+=2;
CREG++;
if (CREG > 0xFF)
{
CREG = 0;
BREG = (BREG+1) & 0xFF;
}
break;
case 0x04: // INC B
numCycles++;
FREG = FLAG_INC[BREG] | (FREG & CARRY);
BREG = (BREG+1) & 0xFF;
break;
case 0x05: // DEC B
numCycles++;
FREG = FLAG_DEC[BREG] | (FREG & CARRY);
BREG = (BREG-1) & 0xFF;
break;
case 0x06: //LD B,n
numCycles+=2;
BREG = readMem(PC++);
break;
case 0x07: // RLCA
numCycles++;
FREG = (AREG & BIT7) >> 3;
AREG = ((AREG << 1) | (AREG >> 7)) & 0xFF;
break;
case 0x08: //LD (nn),SP
numCycles+=5;
index = readMem(PC++) | (readMem(PC++) << 8);
writeMem(index, SP & 0x00FF);
writeMem(index+1, SP >> 8);
break;
case 0x09: // ADD HL,BC
numCycles+=2;
FREG &= ZERO;
LREG += CREG;
HREG += BREG + (LREG >> 8);
LREG &= 0xFF;
if (HREG > 0xFF)
{
HREG &= 0xFF;
FREG |= CARRY;
}
break;
case 0x0A: //LD A,(BC)
numCycles+=2;
AREG = readMem( (BREG << 8) | CREG );
break;
case 0x0B: // DEC BC
numCycles+=2;
CREG--;
if (CREG < 0)
{
CREG = 0xFF;
BREG = (BREG-1) & 0xFF;
}
break;
case 0x0C: // INC C
numCycles++;
FREG = FLAG_INC[CREG] | (FREG & CARRY);
CREG = (CREG+1) & 0xFF;
break;
case 0x0D: // DEC C
numCycles++;
FREG = FLAG_DEC[CREG] | (FREG & CARRY);
CREG = (CREG-1) & 0xFF;
break;
case 0x0E: //LD C,n
numCycles+=2;
CREG=readMem(PC++);
break;
case 0x0F: // RRCA
numCycles++;
FREG = (AREG & BIT0) << 4;
AREG = ((AREG >> 1) | (AREG << 7)) & 0xFF;
break;
case 0x10: // STOP
numCycles++;
//PC++? (not all assemblers insert 0x00)
// *TODO: give control to key listener*
break;
case 0x11: //LD DE,nn
numCycles+=3;
EREG = readMem(PC++);
DREG = readMem(PC++);
break;
case 0x12: //LD (DE),A
numCycles+=2;
writeMem( (DREG << 8) | EREG, AREG);
break;
case 0x13: // INC DE
numCycles+=2;
EREG++;
if (EREG > 0xFF)
{
EREG = 0;
DREG = (DREG+1) & 0xFF;
}
break;
case 0x14: // INC D
numCycles++;
FREG = FLAG_INC[DREG] | (FREG & CARRY);
DREG = (DREG+1) & 0xFF;
break;
case 0x15: // DEC D
numCycles++;
FREG = FLAG_DEC[DREG] | (FREG & CARRY);
DREG = (DREG-1) & 0xFF;
break;
case 0x16: //LD D,n
numCycles+=2;
DREG=readMem(PC++);
break;
case 0x17: // RLA
numCycles++;
val = (FREG & CARRY) >> 4;
FREG = (AREG & BIT7) >> 3;
AREG = ((AREG << 1) | val) & 0xFF;
break;
case 0x18: // JR n
numCycles+=3;
PC += (byte)readMem(PC) + 1; // signed immediate
break;
case 0x19: // ADD HL,DE
numCycles+=2;
FREG &= ZERO;
LREG += EREG;
HREG += DREG + (LREG >> 8);
LREG &= 0xFF;
if (HREG > 0xFF)
{
HREG &= 0xFF;
FREG |= CARRY;
}
break;
case 0x1A: //LD A,(DE)
numCycles+=2;
AREG = readMem( ( DREG << 8 ) | EREG );
break;
case 0x1B: // DEC DE
numCycles+=2;
EREG--;
if (EREG < 0)
{
EREG = 0xFF;
DREG = (DREG-1) & 0xFF;
}
break;
case 0x1C: // INC E
numCycles++;
FREG = FLAG_INC[EREG] | (FREG & CARRY);
EREG = (EREG+1) & 0xFF;
break;
case 0x1D: // DEC E
numCycles++;
FREG = FLAG_DEC[EREG] | (FREG & CARRY);
EREG = (EREG-1) & 0xFF;
break;
case 0x1E: //LD E,n
numCycles+=2;
EREG=readMem(PC++);
break;
case 0x1F: // RRA
numCycles++;
val = (FREG & CARRY) << 3;
FREG = (AREG & BIT0) << 4;
AREG = (AREG >> 1) | val;
break;
case 0x20: // JR NZ,n
if ((FREG & ZERO) == 0)
{
numCycles+=3;
PC += (byte)readMem(PC) + 1; // signed immediate
}
else
{
numCycles+=2;
PC++;
}
break;
case 0x21: //LD HL,nn
numCycles+=3;
LREG = readMem(PC++);
HREG = readMem(PC++);
break;
case 0x22: //LDI (HL),A
numCycles+=2;
index = (HREG << 8) | LREG;
writeMem(index, AREG);
index = (index+1) & 0xFFFF;
HREG = index >> 8;
LREG = index & 0x00FF;
break;
case 0x23: // INC HL
numCycles+=2;
LREG++;
if (LREG > 0xFF)
{
LREG = 0;
HREG = (HREG+1) & 0xFF;
}
break;
case 0x24: // INC H
numCycles++;
FREG = FLAG_INC[HREG] | (FREG & CARRY);
HREG = (HREG+1) & 0xFF;
break;
case 0x25: // DEC H
numCycles++;
FREG = FLAG_DEC[HREG] | (FREG & CARRY);
HREG = (HREG-1) & 0xFF;
break;
case 0x26: //LD H,n
numCycles+=2;
HREG=readMem(PC++);
break;
case 0x27: // DAA
numCycles++;
if ((FREG & SUBTRACT) != 0)
{
if ((AREG & 0x0F) > 0x09 || (FREG & HALF_CARRY) != 0)
AREG -= 0x06;
if ((AREG & 0xF0) > 0x90 || (FREG & CARRY) != 0)
{
AREG -= 0x60;
FREG |= CARRY;
}
else
FREG &= ~CARRY;
}
else
{
if ((AREG & 0x0F) > 0x09 || (FREG & HALF_CARRY) != 0)
AREG += 0x06;
if ((AREG & 0xF0) > 0x90 || (FREG & CARRY) != 0)
{
AREG += 0x60;
FREG |= CARRY;
}
else
FREG &= ~CARRY;
}
FREG &= ~HALF_CARRY;
AREG &= 0xFF;
if (AREG == 0)
FREG |= ZERO;
else
FREG &= ~ZERO;
break;
case 0x28: // JR Z,n
if ((FREG & ZERO) != 0)
{
numCycles+=3;
PC += (byte)readMem(PC) + 1; // signed immediate
}
else
{
numCycles+=2;
PC++;
}
break;
case 0x29: // ADD HL,HL
numCycles+=2;
FREG &= ZERO;
LREG += LREG;
HREG += HREG + (LREG >> 8);
LREG &= 0xFF;
if (HREG > 0xFF)
{
HREG &= 0xFF;
FREG |= CARRY;
}
break;
case 0x2A: //LDI A,(HL)
numCycles+=2;
index = (HREG << 8) | LREG;
AREG = readMem(index);
index = (index+1) & 0xFFFF;
HREG = index >> 8;
LREG = index & 0x00FF;
break;
case 0x2B: // DEC HL
numCycles+=2;
LREG--;
if (LREG < 0)
{
LREG = 0xFF;
HREG = (HREG-1) & 0xFF;
}
break;
case 0x2C: // INC L
numCycles++;
FREG = FLAG_INC[LREG] | (FREG & CARRY);
LREG = (LREG+1) & 0xFF;
break;
case 0x2D: // DEC L
numCycles++;
FREG = FLAG_DEC[LREG] | (FREG & CARRY);
LREG = (LREG-1) & 0xFF;
break;
case 0x2E: //LD L,n
numCycles+=2;
LREG=readMem(PC++);
break;
case 0x2F: // CPL
numCycles++;
FREG |= (SUBTRACT | HALF_CARRY);
AREG ^= 0xFF; // faster than (~AREG) & 0xFF
break;
case 0x30: // JR NC,n
if ((FREG & CARRY) == 0)
{
numCycles+=3;
PC += (byte)readMem(PC) + 1; // signed immediate
}
else
{
numCycles+=2;
PC++;
}
break;
case 0x31: //LD SP,nn
numCycles+=3;
SP = readMem(PC++) | (readMem(PC++) << 8);
break;
case 0x32: //LDD (HL),A
numCycles+=2;
index = (HREG << 8) | LREG;
writeMem(index, AREG);
index = (index-1) & 0xFFFF;
HREG = index >> 8;
LREG = index & 0x00FF;
break;
case 0x33: // INC SP
numCycles+=2;
SP = (SP+1) & 0xFFFF;
break;
case 0x34: // INC (HL)
numCycles+=3;
index = (HREG << 8) | LREG;
memval = readMem(index);
FREG = FLAG_INC[memval] | (FREG & CARRY);
writeMem(index, (memval + 1) & 0xFF);
break;
case 0x35: // DEC (HL)
numCycles+=3;
index = (HREG << 8) | LREG;
memval = readMem(index);
FREG = FLAG_DEC[memval] | (FREG & CARRY);
writeMem(index, (memval - 1) & 0xFF);
break;
case 0x36: //LD (HL),n
numCycles+=3;
writeMem( (HREG << 8) | LREG, readMem(PC++));
break;
case 0x37: // SCF
numCycles++;
FREG &= ~(SUBTRACT | HALF_CARRY);
FREG |= CARRY;
break;
case 0x38: // JR C,n
if ((FREG & CARRY) != 0)
{
numCycles+=3;
PC += (byte)readMem(PC) + 1; // signed immediate
}
else
{
numCycles+=2;
PC++;
}
break;
case 0x39: // ADD HL,SP
numCycles+=2;
FREG &= ZERO;
val = ((HREG << 8) | LREG) + SP;
if (val > 0xFFFF)
{
val &= 0xFFFF;
FREG |= CARRY;
}
HREG = val >> 8;
LREG = val & 0xFF;
break;
case 0x3A: //LDD A,(HL)
numCycles+=2;
index = (HREG << 8) | LREG;
AREG = readMem(index);
index = (index-1) & 0xFFFF;
HREG = index >> 8;
LREG = index & 0x00FF;
break;
case 0x3B: // DEC SP
numCycles+=2;
SP = (SP-1) & 0xFFFF;
break;
case 0x3C: // INC A
numCycles++;
FREG = FLAG_INC[AREG] | (FREG & CARRY);
AREG = (AREG+1) & 0xFF;
break;
case 0x3D: // DEC A
numCycles++;
FREG = FLAG_DEC[AREG] | (FREG & CARRY);
AREG = (AREG-1) & 0xFF;
break;
case 0x3E: //LD A,n
numCycles+=2;
AREG = readMem(PC++);
break;
case 0x3F: // CCF
numCycles++;
FREG &= ~(SUBTRACT | HALF_CARRY);
FREG ^= CARRY;
break;
case 0x40: //LD B,B
numCycles++;
break;
case 0x41: //LD B,C
numCycles++;
BREG=CREG;
break;
case 0x42: //LD B,D
numCycles++;
BREG=DREG;
break;
case 0x43: //LD B,E
numCycles++;
BREG=EREG;
break;
case 0x44: //LD B,H
numCycles++;
BREG=HREG;
break;
case 0x45: //LD B,L
numCycles++;
BREG=LREG;
break;
case 0x46: //LD B,(HL)
numCycles+=2;
BREG=readMem( ( HREG << 8) | LREG );
break;
case 0x47: //LD B,A
numCycles++;
BREG=AREG;
break;
case 0x48: //LD C,B
numCycles++;
CREG=BREG;
break;
case 0x49: //LD C,C
numCycles++;
break;
case 0x4A: //LD C,D
numCycles++;
CREG=DREG;
break;
case 0x4B: //LD C,E
numCycles++;
CREG=EREG;
break;
case 0x4C: //LD C,H
numCycles++;
CREG=HREG;
break;
case 0x4D: //LD C,L
numCycles++;
CREG=LREG;
break;
case 0x4E: //LD C,(HL)
numCycles+=2;