Merge version 1.2 of UART module to master. #2
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Owner
jakubcabal
commented
Dec 23, 2019
jakubcabal
commented
- Added double FF for safe CDC.
- Fixed fake received transaction after FPGA boot without reset.
- Added more precisely clock dividers, dividing with rounding.
- UART loopback example is for CYC1000 board now.
jakubcabal
changed the title
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