Update README.md

Author: jakubcabal

README.md

@@ -10,7 +10,7 @@ The UART controller was simulated and tested in hardware.
 
 ### Generics:
 
-```
+```vhdl
 CLK_FREQ      : integer := 50e6;   -- system clock frequency in Hz
 BAUD_RATE     : integer := 115200; -- baud rate value
 PARITY_BIT    : string  := "none"; -- type of parity: "none", "even", "odd", "mark", "space"
@@ -19,7 +19,7 @@ USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
 
 ### Inputs and outputs ports:
 
-```
+```vhdl
 -- CLOCK AND RESET
 CLK          : in  std_logic; -- system clock
 RST          : in  std_logic; -- high active synchronous reset
@@ -50,10 +50,10 @@ Example of receiving data on the user interface of the UART controller. The last
 ### Table of resource usage summary:
 
 Parity type | LE | FF | M9k | Fmax
-:---:|:---:|:---:|:---:|:---:
-none       | 77 | 56 | 0 | 305.5 MHz
-even/odd   | 84 | 60 | 0 | 289.4 MHz
-mark/space | 82 | 60 | 0 | 290.7 MHz
+------------|----|----|-----|-----------
+none        | 77 | 56 | 0   | 305.5 MHz
+even/odd    | 84 | 60 | 0   | 289.4 MHz
+mark/space  | 82 | 60 | 0   | 290.7 MHz
 
 *Implementation was performed using Quartus Prime Lite Edition 20.1.0 for Intel Cyclone 10 FPGA (10CL025YU256C8G). Setting of some generics: USE_DEBOUNCER = True, BAUD_RATE = 115200, CLK_FREQ = 50e6.*
 
@@ -64,6 +64,13 @@ A simulation is prepared in the repository. You can use the prepared TCL script
 vsim -do sim/sim.tcl
 ```
 
+Or it is possible to run the simulation using the [GHDL tool](https://github.com/ghdl/ghdl). Linux users can use the prepared bash script (in ```sim/``` folder) to run the simulation in GHDL:
+```
+./sim_ghdl_run.sh
+```
+
+I also use the GHDL tool for CI: automated VHDL simulations in the GitHub Actions environment ([setup-ghdl-ci](https://github.com/ghdl/setup-ghdl-ci)).
+
 ## Examples:
 
 The repository also includes several UART example designs. I use it on my [FPGA board CYC1000](https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM) with Intel Cyclone 10 FPGA (10CL025YU256C8G) and FTDI USB to UART Bridge. Here you can find [the documentation of the CYC1000 board](https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0003/REV02/Documents/CYC1000%20User%20Guide.pdf).