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LOOPBACK EXAMPLE [MAINTENANCE]: Update subcomponents in example design
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‎example/comp/btn_debounce.vhd

Lines changed: 70 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,100 @@
11
--------------------------------------------------------------------------------
2-
-- PROJECT: FPGA MISC
2+
-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
33
--------------------------------------------------------------------------------
4-
-- NAME: BTN_DEBOUNCE
54
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
6-
-- LICENSE: The MIT License
7-
-- WEBSITE: https://github.com/jakubcabal/fpga-misc
5+
-- LICENSE: LGPL-3.0, please read LICENSE file
6+
-- WEBSITE: https://github.com/jakubcabal/spi-fpga
87
--------------------------------------------------------------------------------
98

109
library IEEE;
1110
use IEEE.STD_LOGIC_1164.ALL;
1211
use IEEE.NUMERIC_STD.ALL;
1312

1413
entity BTN_DEBOUNCE is
14+
Generic (
15+
CNT_WIDTH : natural := 2 -- width of debounce counter
16+
);
1517
Port (
16-
CLK : in std_logic; -- system clock
17-
CLK_EN_1K : in std_logic; -- clock enable 1 KHz
18-
ASYNC_RST : in std_logic; -- asynchrounous reset
19-
BTN_RAW : in std_logic; -- button raw signal
20-
BTN_DEB : out std_logic; -- button debounce signal
21-
BTN_DEB_EN : out std_logic -- button debounce rising edge enable
18+
CLK : in std_logic; -- system clock
19+
ASYNC_RST : in std_logic; -- asynchrounous reset
20+
SAMPLE_EN : in std_logic; -- sample clock enable
21+
BTN_RAW : in std_logic; -- button raw signal
22+
BTN_DEB : out std_logic; -- button debounce signal
23+
BTN_DEB_RE : out std_logic -- rising edge of debounced signal
2224
);
23-
end BTN_DEBOUNCE;
25+
end entity;
2426

2527
architecture RTL of BTN_DEBOUNCE is
2628

27-
signal btn_raw_shreg : std_logic_vector(3 downto 0);
28-
signal btn_deb_comb : std_logic;
29-
signal btn_deb_reg : std_logic;
30-
signal btn_deb_en_reg : std_logic;
29+
signal btn_raw_sync_reg1 : std_logic;
30+
signal btn_raw_sync_reg2 : std_logic;
31+
signal btn_raw_sample_reg : std_logic;
32+
signal btn_raw_diff : std_logic;
33+
signal deb_cnt : unsigned(CNT_WIDTH-1 downto 0);
34+
signal deb_cnt_max : std_logic;
35+
signal btn_deb_reg : std_logic;
36+
signal btn_deb_re_reg : std_logic;
3137

3238
begin
3339

3440
-- -------------------------------------------------------------------------
35-
-- SHIFT REGISTER OF BUTTON RAW SIGNAL
41+
-- BUTTON RAW SIGNAL SYNCHRONIZATION REGISTERS
3642
-- -------------------------------------------------------------------------
3743

38-
btn_shreg_p : process (CLK, ASYNC_RST)
44+
btn_raw_sync_reg_p : process (CLK)
3945
begin
40-
if (ASYNC_RST = '1') then
41-
btn_raw_shreg <= (others => '0');
42-
elsif (rising_edge(CLK)) then
43-
if (CLK_EN_1K = '1') then
44-
btn_raw_shreg <= btn_raw_shreg(2 downto 0) & BTN_RAW;
45-
end if;
46+
if (rising_edge(CLK)) then
47+
btn_raw_sync_reg1 <= BTN_RAW;
48+
btn_raw_sync_reg2 <= btn_raw_sync_reg1;
4649
end if;
4750
end process;
4851

4952
-- -------------------------------------------------------------------------
50-
-- DEBOUNCE REGISTER OF BUTTON RAW SIGNAL
53+
-- BUTTON RAW SIGNAL SAMPLE REGISTERS
5154
-- -------------------------------------------------------------------------
5255

53-
btn_deb_comb <= btn_raw_shreg(0) and btn_raw_shreg(1) and
54-
btn_raw_shreg(2) and btn_raw_shreg(3);
56+
btn_raw_sample_reg_p : process (CLK)
57+
begin
58+
if (rising_edge(CLK)) then
59+
if (SAMPLE_EN = '1') then
60+
btn_raw_sample_reg <= btn_raw_sync_reg2;
61+
end if;
62+
end if;
63+
end process;
64+
65+
btn_raw_diff <= btn_raw_sample_reg xor btn_raw_sync_reg2;
5566

56-
btn_deb_reg_p : process (CLK, ASYNC_RST)
67+
-- -------------------------------------------------------------------------
68+
-- DEBOUNCE COUNTER
69+
-- -------------------------------------------------------------------------
70+
71+
deb_cnt_p : process (CLK, ASYNC_RST)
5772
begin
5873
if (ASYNC_RST = '1') then
59-
btn_deb_reg <= '0';
74+
deb_cnt <= (others => '0');
6075
elsif (rising_edge(CLK)) then
61-
btn_deb_reg <= btn_deb_comb;
76+
if (SAMPLE_EN = '1') then
77+
if (btn_raw_diff = '1') then
78+
deb_cnt <= (others => '0');
79+
else
80+
deb_cnt <= deb_cnt + 1;
81+
end if;
82+
end if;
83+
end if;
84+
end process;
85+
86+
deb_cnt_max <= '1' when (deb_cnt = (2**CNT_WIDTH)-1) else '0';
87+
88+
-- -------------------------------------------------------------------------
89+
-- BUTTON DEBOUNCE SIGNAL REGISTER
90+
-- -------------------------------------------------------------------------
91+
92+
btn_deb_reg_p : process (CLK)
93+
begin
94+
if (rising_edge(CLK)) then
95+
if (deb_cnt_max = '1') then
96+
btn_deb_reg <= btn_raw_sample_reg;
97+
end if;
6298
end if;
6399
end process;
64100

@@ -68,15 +104,15 @@ begin
68104
-- RISING EDGE DETECTOR OF BUTTON DEBOUNCE SIGNAL
69105
-- -------------------------------------------------------------------------
70106

71-
sseg_an_cnt_p : process (CLK, ASYNC_RST)
107+
btn_deb_re_reg_p : process (CLK, ASYNC_RST)
72108
begin
73109
if (ASYNC_RST = '1') then
74-
btn_deb_en_reg <= '0';
110+
btn_deb_re_reg <= '0';
75111
elsif (rising_edge(CLK)) then
76-
btn_deb_en_reg <= btn_deb_comb and not btn_deb_reg;
112+
btn_deb_re_reg <= deb_cnt_max and btn_raw_sample_reg and not btn_deb_reg;
77113
end if;
78114
end process;
79115

80-
BTN_DEB_EN <= btn_deb_en_reg;
116+
BTN_DEB_RE <= btn_deb_re_reg;
81117

82-
end RTL;
118+
end architecture;

‎example/comp/clk_en_gen.vhd

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
11
--------------------------------------------------------------------------------
2-
-- PROJECT: FPGA MISC
2+
-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
33
--------------------------------------------------------------------------------
4-
-- NAME: CLK_EN_GEN
54
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
6-
-- LICENSE: The MIT License
7-
-- WEBSITE: https://github.com/jakubcabal/fpga-misc
5+
-- LICENSE: LGPL-3.0, please read LICENSE file
6+
-- WEBSITE: https://github.com/jakubcabal/spi-fpga
87
--------------------------------------------------------------------------------
98

109
library IEEE;

‎example/comp/rst_sync.vhd

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
--------------------------------------------------------------------------------
2+
-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
3+
--------------------------------------------------------------------------------
4+
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5+
-- LICENSE: LGPL-3.0, please read LICENSE file
6+
-- WEBSITE: https://github.com/jakubcabal/spi-fpga
7+
--------------------------------------------------------------------------------
8+
9+
library IEEE;
10+
use IEEE.STD_LOGIC_1164.ALL;
11+
use IEEE.NUMERIC_STD.ALL;
12+
13+
entity RST_SYNC is
14+
Port (
15+
CLK : in std_logic;
16+
ASYNC_RST : in std_logic;
17+
SYNCED_RST : out std_logic
18+
);
19+
end entity;
20+
21+
architecture RTL of RST_SYNC is
22+
23+
attribute ALTERA_ATTRIBUTE : string;
24+
attribute PRESERVE : boolean;
25+
26+
signal meta_reg : std_logic;
27+
signal reset_reg : std_logic;
28+
29+
attribute ALTERA_ATTRIBUTE of RTL : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*RST_SYNC:*|meta_reg}] """;
30+
attribute ALTERA_ATTRIBUTE of meta_reg : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
31+
attribute ALTERA_ATTRIBUTE of reset_reg : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
32+
attribute PRESERVE of meta_reg : signal is TRUE;
33+
attribute PRESERVE of reset_reg : signal is TRUE;
34+
35+
begin
36+
37+
process (CLK, ASYNC_RST)
38+
begin
39+
if (ASYNC_RST = '1') then
40+
meta_reg <= '1';
41+
reset_reg <= '1';
42+
elsif (rising_edge(CLK)) then
43+
meta_reg <= '0';
44+
reset_reg <= meta_reg;
45+
end if;
46+
end process;
47+
48+
SYNCED_RST <= reset_reg;
49+
50+
end architecture;

‎example/comp/sseg_driver.vhd

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
11
--------------------------------------------------------------------------------
2-
-- PROJECT: FPGA MISC
2+
-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
33
--------------------------------------------------------------------------------
4-
-- NAME: SSEG_DRIVER
54
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
6-
-- LICENSE: The MIT License
7-
-- WEBSITE: https://github.com/jakubcabal/fpga-misc
5+
-- LICENSE: LGPL-3.0, please read LICENSE file
6+
-- WEBSITE: https://github.com/jakubcabal/spi-fpga
87
--------------------------------------------------------------------------------
98

109
library IEEE;

‎example/quartus/spi_loopback_ep4ce6sb.qpf

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,5 @@
55
# LICENSE: LGPL-3.0, please read LICENSE file
66
# WEBSITE: https://github.com/jakubcabal/spi-fpga
77
#-------------------------------------------------------------------------------
8-
# COPYRIGHT NOTICE:
9-
#-------------------------------------------------------------------------------
10-
# SPI MASTER AND SLAVE FOR FPGA
11-
# Copyright (C) 2020 Jakub Cabal
12-
#
13-
# This source file is free software: you can redistribute it and/or modify
14-
# it under the terms of the GNU Lesser General Public License as published by
15-
# the Free Software Foundation, either version 3 of the License, or
16-
# (at your option) any later version.
17-
#
18-
# This source file is distributed in the hope that it will be useful,
19-
# but WITHOUT ANY WARRANTY; without even the implied warranty of
20-
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21-
# GNU Lesser General Public License for more details.
22-
#
23-
# You should have received a copy of the GNU Lesser General Public License
24-
# along with this program. If not, see <http://www.gnu.org/licenses/>.
25-
#-------------------------------------------------------------------------------
268

279
PROJECT_REVISION = "spi_loopback_ep4ce6sb"

‎example/quartus/spi_loopback_ep4ce6sb.qsf

Lines changed: 1 addition & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5,24 +5,6 @@
55
# LICENSE: LGPL-3.0, please read LICENSE file
66
# WEBSITE: https://github.com/jakubcabal/spi-fpga
77
#-------------------------------------------------------------------------------
8-
# COPYRIGHT NOTICE:
9-
#-------------------------------------------------------------------------------
10-
# SPI MASTER AND SLAVE FOR FPGA
11-
# Copyright (C) 2020 Jakub Cabal
12-
#
13-
# This source file is free software: you can redistribute it and/or modify
14-
# it under the terms of the GNU Lesser General Public License as published by
15-
# the Free Software Foundation, either version 3 of the License, or
16-
# (at your option) any later version.
17-
#
18-
# This source file is distributed in the hope that it will be useful,
19-
# but WITHOUT ANY WARRANTY; without even the implied warranty of
20-
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21-
# GNU Lesser General Public License for more details.
22-
#
23-
# You should have received a copy of the GNU Lesser General Public License
24-
# along with this program. If not, see <http://www.gnu.org/licenses/>.
25-
#-------------------------------------------------------------------------------
268

279
# GLOBAL CONSTRAINTS FOR EP4CE6 STARTER BOARD
2810

@@ -33,6 +15,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY SPI_LOOPBACK
3315
# PROJECT VHDL FILES
3416
set_global_assignment -name VHDL_FILE ../../rtl/spi_slave.vhd
3517
set_global_assignment -name VHDL_FILE ../../rtl/spi_master.vhd
18+
set_global_assignment -name VHDL_FILE ../comp/rst_sync.vhd
3619
set_global_assignment -name VHDL_FILE ../comp/clk_en_gen.vhd
3720
set_global_assignment -name VHDL_FILE ../comp/sseg_driver.vhd
3821
set_global_assignment -name VHDL_FILE ../comp/btn_debounce.vhd

‎example/quartus/spi_loopback_ep4ce6sb.sdc

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,5 @@
55
# LICENSE: LGPL-3.0, please read LICENSE file
66
# WEBSITE: https://github.com/jakubcabal/spi-fpga
77
#-------------------------------------------------------------------------------
8-
# COPYRIGHT NOTICE:
9-
#-------------------------------------------------------------------------------
10-
# SPI MASTER AND SLAVE FOR FPGA
11-
# Copyright (C) 2020 Jakub Cabal
12-
#
13-
# This source file is free software: you can redistribute it and/or modify
14-
# it under the terms of the GNU Lesser General Public License as published by
15-
# the Free Software Foundation, either version 3 of the License, or
16-
# (at your option) any later version.
17-
#
18-
# This source file is distributed in the hope that it will be useful,
19-
# but WITHOUT ANY WARRANTY; without even the implied warranty of
20-
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21-
# GNU Lesser General Public License for more details.
22-
#
23-
# You should have received a copy of the GNU Lesser General Public License
24-
# along with this program. If not, see <http://www.gnu.org/licenses/>.
25-
#-------------------------------------------------------------------------------
268

279
create_clock -name CLK50 -period 20.000 [get_ports {CLK}]

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