LOOPBACK EXAMPLE [MAINTENANCE]: Move example to new folder

Author: jakubcabal

README.md

@@ -101,7 +101,7 @@ SPI SLAVE | 24 | 15 | 0 | 343.7 MHz
 
 The SPI loopback example design is for testing data transfer between SPI master and SPI slave over external wires.
 
-Please read [README file of SPI loopback example design](example/README.md).
+Please read [README file of SPI loopback example design](examples/loopback/README.md).
 
 [![Video of SPI loopback example design](https://img.youtube.com/vi/-TbtB6Sm2Xk/0.jpg)](https://youtu.be/-TbtB6Sm2Xk)
 

example/comp/btn_debounce.vhd renamed to examples/common/btn_debounce.vhd

@@ -13,12 +13,12 @@ set_global_assignment -name DEVICE EP4CE6E22C8
 set_global_assignment -name TOP_LEVEL_ENTITY SPI_LOOPBACK
 
 # PROJECT VHDL FILES
-set_global_assignment -name VHDL_FILE ../../rtl/spi_slave.vhd
-set_global_assignment -name VHDL_FILE ../../rtl/spi_master.vhd
-set_global_assignment -name VHDL_FILE ../comp/rst_sync.vhd
-set_global_assignment -name VHDL_FILE ../comp/clk_en_gen.vhd
-set_global_assignment -name VHDL_FILE ../comp/sseg_driver.vhd
-set_global_assignment -name VHDL_FILE ../comp/btn_debounce.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/spi_slave.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/spi_master.vhd
+set_global_assignment -name VHDL_FILE ../../common/rst_sync.vhd
+set_global_assignment -name VHDL_FILE ../../common/clk_en_gen.vhd
+set_global_assignment -name VHDL_FILE ../../common/sseg_driver.vhd
+set_global_assignment -name VHDL_FILE ../../common/btn_debounce.vhd
 set_global_assignment -name VHDL_FILE ../spi_loopback.vhd
 
 # FPGA PINS ASSIGNMENT