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SPI MASTER [FEATURE]: Add better simulation
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‎sim/spi_master_tb.vhd

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--------------------------------------------------------------------------------
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-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
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--------------------------------------------------------------------------------
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-- NAME: SPI_MASTER
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-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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-- LICENSE: LGPL-3.0, please read LICENSE file
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-- WEBSITE: https://github.com/jakubcabal/spi-fpga
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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entity SPI_MASTER_TB is
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Generic (
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CLK_FREQ : natural := 50e6; -- system clock frequency in Hz
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SPI_FREQ : natural := 1e6; -- spi clock frequency in Hz
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WORD_SIZE : natural := 8; -- size of transfer word in bits, must be power of two
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TRANS_COUNT : natural := 1e4 -- number of test transaction
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);
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end entity;
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architecture SIM of SPI_MASTER_TB is
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constant CLK_PERIOD : time := 1 ns * integer(real(1e9)/real(CLK_FREQ));
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constant SPI_PERIOD : time := 1 ns * integer(real(1e9)/real(SPI_FREQ));
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constant RX_OFFSET : natural := 42;
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constant TX_OFFSET : natural := 11;
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signal CLK : std_logic;
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signal RST : std_logic;
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signal sclk : std_logic;
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signal cs_n : std_logic;
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signal mosi : std_logic;
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signal miso : std_logic;
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signal udi : std_logic_vector(WORD_SIZE-1 downto 0);
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signal udi_vld : std_logic;
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signal udi_rdy : std_logic;
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signal udo : std_logic_vector(WORD_SIZE-1 downto 0);
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signal udo_exp : std_logic_vector(WORD_SIZE-1 downto 0);
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signal udo_vld : std_logic;
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signal spi_sdi : std_logic_vector(WORD_SIZE-1 downto 0);
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signal spi_sdo : std_logic_vector(WORD_SIZE-1 downto 0);
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signal spi_sdo_exp : std_logic_vector(WORD_SIZE-1 downto 0);
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signal spi_model_done : std_logic := '0';
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signal udi_done : std_logic := '0';
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signal udo_done : std_logic := '0';
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signal sim_done : std_logic := '0';
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signal rand_int : integer := 0;
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signal count_rx : integer;
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signal count_tx : integer;
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procedure SPI_SLAVE (
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signal SSM_SDI : in std_logic_vector(WORD_SIZE-1 downto 0);
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signal SSM_SDO : out std_logic_vector(WORD_SIZE-1 downto 0);
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signal SSM_SCLK : in std_logic;
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signal SSM_CS_N : in std_logic;
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signal SSM_MOSI : in std_logic;
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signal SSM_MISO : out std_logic
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) is
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begin
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wait until SSM_CS_N = '0';
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for i in 0 to (WORD_SIZE-1) loop
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SSM_MISO <= SSM_SDI(WORD_SIZE-1-i);
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wait until rising_edge(SSM_SCLK);
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SSM_SDO(WORD_SIZE-1-i) <= SSM_MOSI;
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wait until falling_edge(SSM_SCLK);
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end loop;
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end procedure;
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begin
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rand_int_p : process
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variable seed1, seed2: positive;
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variable rand : real;
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begin
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uniform(seed1, seed2, rand);
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rand_int <= integer(rand*real(20));
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--report "Random number X: " & integer'image(rand_int);
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wait for CLK_PERIOD;
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if (sim_done = '1') then
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wait;
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end if;
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end process;
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dut : entity work.SPI_MASTER
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generic map (
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CLK_FREQ => CLK_FREQ,
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SCLK_FREQ => SPI_FREQ,
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WORD_SIZE => WORD_SIZE
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)
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port map (
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CLK => CLK,
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RST => RST,
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-- SPI SLAVE INTERFACE
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SCLK => sclk,
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CS_N(0) => cs_n,
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MOSI => mosi,
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MISO => miso,
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-- USER INTERFACE
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DIN => udi,
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DIN_ADDR => (others => '0'),
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DIN_LAST => '1',
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DIN_VLD => udi_vld,
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DIN_RDY => udi_rdy,
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DOUT => udo,
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DOUT_VLD => udo_vld
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);
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clk_gen_p : process
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begin
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CLK <= '0';
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wait for CLK_PERIOD/2;
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CLK <= '1';
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wait for CLK_PERIOD/2;
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if (sim_done = '1') then
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wait;
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end if;
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end process;
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rst_gen_p : process
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begin
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report "======== SIMULATION START! ========";
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report "Total transactions for master to slave direction: " & integer'image(TRANS_COUNT);
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report "Total transactions for slave to master direction: " & integer'image(TRANS_COUNT);
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RST <= '1';
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wait for CLK_PERIOD*3;
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RST <= '0';
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wait;
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end process;
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-- -------------------------------------------------------------------------
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-- DUT TEST
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-- -------------------------------------------------------------------------
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spi_slave_model_p : process
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begin
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count_tx <= 1;
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wait until RST = '0';
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for i in 0 to TRANS_COUNT-1 loop
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spi_sdi <= std_logic_vector(to_unsigned(((i+RX_OFFSET) mod 2**WORD_SIZE),WORD_SIZE));
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spi_sdo_exp <= std_logic_vector(to_unsigned(((i+TX_OFFSET) mod 2**WORD_SIZE),WORD_SIZE));
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SPI_SLAVE(spi_sdi, spi_sdo, sclk, cs_n, mosi, miso);
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if (spi_sdo = spi_sdo_exp) then
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if ((count_tx mod (TRANS_COUNT/10)) = 0) then
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report "Transactions received from master: " & integer'image(count_tx);
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end if;
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else
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report "======== UNEXPECTED TRANSACTION ON MOSI SIGNAL (master to slave)! ========" severity failure;
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end if;
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count_tx <= count_tx + 1;
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end loop;
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spi_model_done <= '1';
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wait;
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end process;
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spi_master_udi_p : process
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begin
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wait until RST = '0';
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wait until rising_edge(CLK);
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wait for CLK_PERIOD/2;
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for i in 0 to TRANS_COUNT-1 loop
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udi <= std_logic_vector(to_unsigned(((i+TX_OFFSET) mod 2**WORD_SIZE),WORD_SIZE));
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udi_vld <= '1';
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if (udi_rdy = '0') then
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wait until udi_rdy = '1';
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wait for CLK_PERIOD/2;
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end if;
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wait for CLK_PERIOD;
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udi_vld <= '0';
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wait for rand_int*CLK_PERIOD;
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end loop;
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udi_done <= '1';
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wait;
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end process;
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spi_master_udo_p : process
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begin
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count_rx <= 1;
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for i in 0 to TRANS_COUNT-1 loop
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udo_exp <= std_logic_vector(to_unsigned(((i+RX_OFFSET) mod 2**WORD_SIZE),WORD_SIZE));
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wait until udo_vld = '1';
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if (udo = udo_exp) then
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if ((count_rx mod (TRANS_COUNT/10)) = 0) then
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report "Transactions received from slave: " & integer'image(count_rx);
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end if;
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else
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report "======== UNEXPECTED TRANSACTION ON DOUT SIGNAL (slave to master)! ========" severity failure;
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end if;
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count_rx <= count_rx + 1;
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wait for CLK_PERIOD;
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end loop;
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udo_done <= '1';
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wait;
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end process;
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-- -------------------------------------------------------------------------
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-- TEST DONE CHECK
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-- -------------------------------------------------------------------------
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test_done_p : process
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variable v_test_done : std_logic;
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begin
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v_test_done := spi_model_done and udi_done and udo_done;
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if (v_test_done = '1') then
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wait for 100*CLK_PERIOD;
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sim_done <= '1';
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report "======== SIMULATION SUCCESSFULLY COMPLETED! ========";
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wait;
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end if;
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wait for CLK_PERIOD;
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end process;
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end architecture;

‎sim/spi_master_tb_msim_run.tcl

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#-------------------------------------------------------------------------------
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# PROJECT: SPI MASTER AND SLAVE FOR FPGA
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#-------------------------------------------------------------------------------
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# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
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# LICENSE: LGPL-3.0, please read LICENSE file
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# WEBSITE: https://github.com/jakubcabal/spi-fpga
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#-------------------------------------------------------------------------------
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# Create work library
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vlib work
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# Compile VHDL files
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vcom -93 ../rtl/spi_master.vhd
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vcom -93 ./spi_master_tb.vhd
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# Load testbench
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vsim work.spi_master_tb
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# Setup and start simulation
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add wave sim:/spi_master_tb/*
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add wave sim:/spi_master_tb/dut/*
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run -All

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