SPI SLAVE [FEATURE]: Add WORD_SIZE generic

Author: jakubcabal

rtl/spi_slave.vhd

@@ -28,10 +28,14 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
 
 -- THE SPI SLAVE MODULE SUPPORT ONLY SPI MODE 0 (CPOL=0, CPHA=0)!!!
 
 entity SPI_SLAVE is
+    Generic(
+        WORD_SIZE : natural := 8 -- size of transfer word in bits, must be power of two
+    );
     Port (
         CLK      : in  std_logic; -- system clock
         RST      : in  std_logic; -- high active synchronous reset
@@ -41,24 +45,26 @@ entity SPI_SLAVE is
         MOSI     : in  std_logic; -- SPI serial data from master to slave
         MISO     : out std_logic; -- SPI serial data from slave to master
         -- USER INTERFACE
-        DIN      : in  std_logic_vector(7 downto 0); -- input data for SPI master
+        DIN      : in  std_logic_vector(WORD_SIZE-1 downto 0); -- input data for SPI master
         DIN_VLD  : in  std_logic; -- when DIN_VLD = 1, input data are valid
         DIN_RDY  : out std_logic; -- when DIN_RDY = 1, valid input data are accept
-        DOUT     : out std_logic_vector(7 downto 0); -- output data from SPI master
+        DOUT     : out std_logic_vector(WORD_SIZE-1 downto 0); -- output data from SPI master
         DOUT_VLD : out std_logic  -- when DOUT_VLD = 1, output data are valid
     );
 end SPI_SLAVE;
 
 architecture RTL of SPI_SLAVE is
 
+    constant BIT_CNT_WIDTH : natural := natural(ceil(log2(real(WORD_SIZE))));
+
     signal spi_clk_reg        : std_logic;
     signal spi_clk_redge_en   : std_logic;
     signal spi_clk_fedge_en   : std_logic;
-    signal bit_cnt            : unsigned(2 downto 0);
+    signal bit_cnt            : unsigned(BIT_CNT_WIDTH-1 downto 0);
     signal bit_cnt_max        : std_logic;
     signal last_bit_en        : std_logic;
     signal load_data_en       : std_logic;
-    signal data_shreg         : std_logic_vector(7 downto 0);
+    signal data_shreg         : std_logic_vector(WORD_SIZE-1 downto 0);
     signal slave_ready        : std_logic;
     signal shreg_busy         : std_logic;
     signal rx_data_vld        : std_logic;
@@ -112,7 +118,7 @@ begin
     end process;
 
     -- The flag of maximal value of the bit counter.
-    bit_cnt_max <= '1' when (bit_cnt = "111") else '0';
+    bit_cnt_max <= '1' when (bit_cnt = WORD_SIZE-1) else '0';
 
     -- -------------------------------------------------------------------------
     --  LAST BIT FLAG REGISTER
@@ -181,7 +187,7 @@ begin
             if (load_data_en = '1') then
                 data_shreg <= DIN;
             elsif (spi_clk_redge_en = '1' and CS_N = '0') then
-                data_shreg <= data_shreg(6 downto 0) & MOSI;
+                data_shreg <= data_shreg(WORD_SIZE-2 downto 0) & MOSI;
             end if;
         end if;
     end process;
@@ -196,9 +202,9 @@ begin
     begin
         if (rising_edge(CLK)) then
             if (load_data_en = '1') then
-                MISO <= DIN(7);
+                MISO <= DIN(WORD_SIZE-1);
             elsif (spi_clk_fedge_en = '1' and CS_N = '0') then
-                MISO <= data_shreg(7);
+                MISO <= data_shreg(WORD_SIZE-1);
             end if;
         end if;
     end process;