SPI [MAINTENANCE]: Change some code style

Author: jakubcabal

example/spi_loopback.vhd

@@ -49,7 +49,7 @@ entity SPI_LOOPBACK is
         SSEG            : out std_logic_vector(7 downto 0);
         SSEG_AN         : out std_logic_vector(3 downto 0)
     );
-end SPI_LOOPBACK;
+end entity;
 
 architecture RTL of SPI_LOOPBACK is
 
@@ -298,4 +298,4 @@ begin
         SSEG_AN   => SSEG_AN
     );
 
-end RTL;
+end architecture;

rtl/spi_master.vhd

@@ -56,7 +56,7 @@ entity SPI_MASTER is
         DOUT     : out std_logic_vector(7 downto 0); -- output data from SPI slave
         DOUT_VLD : out std_logic  -- when DOUT_VLD = 1, output data are valid
     );
-end SPI_MASTER;
+end entity;
 
 architecture RTL of SPI_MASTER is
 
@@ -352,4 +352,4 @@ begin
         end case;
     end process;
 
-end RTL;
+end architecture;

rtl/spi_slave.vhd

@@ -33,7 +33,7 @@ use IEEE.MATH_REAL.ALL;
 -- THE SPI SLAVE MODULE SUPPORT ONLY SPI MODE 0 (CPOL=0, CPHA=0)!!!
 
 entity SPI_SLAVE is
-    Generic(
+    Generic (
         WORD_SIZE : natural := 8 -- size of transfer word in bits, must be power of two
     );
     Port (
@@ -51,7 +51,7 @@ entity SPI_SLAVE is
         DOUT     : out std_logic_vector(WORD_SIZE-1 downto 0); -- output data from SPI master
         DOUT_VLD : out std_logic  -- when DOUT_VLD = 1, output data are valid
     );
-end SPI_SLAVE;
+end entity;
 
 architecture RTL of SPI_SLAVE is
 
@@ -217,4 +217,4 @@ begin
     DOUT     <= data_shreg;
     DOUT_VLD <= rx_data_vld;
 
-end RTL;
+end architecture;

sim/spi_tb.vhd

@@ -31,7 +31,7 @@ use IEEE.NUMERIC_STD.ALL;
 use IEEE.MATH_REAL.ALL;
 
 entity SPI_TB is
-end SPI_TB;
+end entity;
 
 architecture SIM of SPI_TB is
 
@@ -184,4 +184,4 @@ begin
         wait;
     end process;
 
-end SIM;
+end architecture;